Implementing enhanced dual mode SRAM performance screen ring...

Details Implementing enhanced dual mode SRAM performance screen ring... Implementing enhanced dual mode SRAM performance screen ring...

2009-01-27

2010-11-16

Le, Thong Q (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S189040, C365S230030, C365S230080, C365S189080, C365S189140

Reexamination Certificate

active

07835176

ABSTRACT:
A method and circuit for implementing an enhanced dual-mode static random access memory (SRAM) performance screen ring oscillator (PSRO), and a design structure on which the subject circuit resides are provided. The dual-mode SRAM PSRO includes a plurality of SRAM base blocks connected together in a chain. Each of the plurality of SRAM base blocks includes an eight-transistor (8T) SRAM cell, a local evaluation circuit and a logic function coupled to the SRAM cell. The eight-transistor (8T) static random access memory (SRAM) cell is an unmodified 8T SRAM cell. The dual-mode SRAM PSRO includes one mode of operation, where the output frequency is determined by write-through performance of the 8T SRAM cell; and another mode of operation, where the output frequency is determined by read performance of the 8T SRAM cell.

REFERENCES:
patent: 6370073 (2002-04-01), Leung
patent: 7082067 (2006-07-01), Venkatraman et al.
patent: 7142064 (2006-11-01), Chan et al.
U.S. Appl. No. 11/782,808, filed Jul. 25, 2007, by Chad Allen Adams, Todd Alan Christensen, Travis Reynold Hebig, and Kirk David Peterson, entitled “Method and Apparatus for Implementing Enhanced SRAM Read Performance Sort Ring Oscillator (PSRO)”.

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