Implementing CML multiplexer load balancing

Details Implementing CML multiplexer load balancing Implementing CML multiplexer load balancing

2009-02-05

2010-10-12

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C327S108000

Reexamination Certificate

active

07812643

ABSTRACT:
A method and current mode logic (CML) multiplexer circuit for implementing load balancing, and a design structure on which the subject circuit resides are provided. CML multiplexer circuit includes first and second differential transistor pairs receiving a first differential input signal and a second differential input signal. The respective transistors of the first and second differential transistor pairs are connected to respective differential signal first and second outputs. CML multiplexer circuit includes load balancing third and fourth differential transistor pairs receiving the first differential input signal and the second differential input signal. The respective transistors of the load balancing third and fourth differential transistor pairs are connected to the opposite differential signal outputs as the first and second differential transistor pairs and the select devices are turned off, matching the source impedance of the unselected first or second differential transistor pair.

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patent: 2009/0252215 (2009-10-01), Bulzacchelli et al.
patent: 2009/0259781 (2009-10-01), Padaparambil

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