Implementing at-speed Wafer Final Test (WFT) with complete...

Details Implementing at-speed Wafer Final Test (WFT) with complete... Implementing at-speed Wafer Final Test (WFT) with complete...

2009-04-24

2010-12-14

Nguyen, Ha Tran T (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S527000, C324S1540PB, C716S030000, C438S014000, C257S048000

Reexamination Certificate

active

07852103

ABSTRACT:
A method, an apparatus and a computer program product are provided for implementing At-Speed Wafer Final Test (WFT) with total integrated circuit chip coverage including high speed off-chip receiver and driver input/output (I/O) circuits. An integrated circuit (IC) chip includes off-chip Controlled Collapse Chip Connection (C4) nodes and a driver and a receiver of the off-chip receiver and driver input/output (I/O) circuits connected to respective off-chip C4 nodes. Through Silicon Vias (TSVs) are added to the connections of the driver and the receiver and the respective off-chip C4 nodes to a backside of the IC chip. A metal wire is added to the IC chip backside connecting the TSVs and creating a connection path between the driver and the receiver that is used for the at-speed WFT testing of the I/O circuits.

REFERENCES:
patent: 7512915 (2009-03-01), Anand et al.
patent: 2008/0210935 (2008-09-01), Ebara

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