Implementing APS voltage level activation with secondary...

Details Implementing APS voltage level activation with secondary... Implementing APS voltage level activation with secondary...

2011-01-04

2011-01-04

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07865859

ABSTRACT:
A method and apparatus implement adaptive power supply (APS) system voltage level activation eliminating the use of electronic Fuses (eFuses), and a design structure on which the subject circuit resides are provided. A primary chip includes an adaptive power supply (APS). A secondary chip circuit includes at least one pair of hard-wired APS setting connections. Each hard-wired APS setting connection is defined by a selected one of a voltage supply connection and a ground potential connection. A respective inverter couples a control signal from each of the hard-wired APS setting connections to a power communication bus connected to the APS on the primary chip.

REFERENCES:
patent: 6388853 (2002-05-01), Balakrishnan et al.
U.S. Appl. No. 11/016,219, to Anthony Bonaccio, filed Dec. 17, 2004, entitled Using Electrically Programmable Fuses To Hide Architecture, Prevent Reverse Engineering, and Make A Device Inoperable.
U.S. Appl. No. 11/016,220, to Karl Erickson, filed Dec. 17, 2004, entitled Changing Chip Function Based on Fuse States.
“Three-dimensional integrated circuits” by A.W. Topol et al., IMB J. Res. & Dev., vol. 50 No. 4/5, pp. 491-501, Jul./Sep. 2006.

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