Implementation of wait-states

Details Implementation of wait-states Implementation of wait-states

2005-10-11

2005-10-11

Butler, Dennis M. (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S601000

Reexamination Certificate

active

06954873

ABSTRACT:
An improved implementation of wait-states in an SOC architecture with optimized performance is described. The clock input signal to the processor is modified during wait-states so that the wait signal does not have to be provided within a short setup time. Data integrity is maintained by providing alternative data paths during wait-states.

REFERENCES:
patent: 5125088 (1992-06-01), Culley
patent: 5546567 (1996-08-01), Nakamura
patent: 5581745 (1996-12-01), Muraoka et al.
patent: 5598556 (1997-01-01), Ghosh et al.
patent: 5838931 (1998-11-01), Regenold et al.
patent: 6216217 (2001-04-01), Seki
patent: 6636907 (2003-10-01), Gaillard et al.
patent: 0690370 (1996-01-01), None
patent: 0690370 (1997-04-01), None

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