Implementation of wait-states

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis

Reexamination Certificate

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C713S601000

Reexamination Certificate

active

06954873

ABSTRACT:
An improved implementation of wait-states in an SOC architecture with optimized performance is described. The clock input signal to the processor is modified during wait-states so that the wait signal does not have to be provided within a short setup time. Data integrity is maintained by providing alternative data paths during wait-states.

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