Implementation of timing between a microprocessor and its periph

Details Implementation of timing between a microprocessor and its periph Implementation of timing between a microprocessor and its periph

1997-05-13

1999-11-02

Palys, Joseph E.

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output addressing

713400, G06F 300

Patent

active

059788593

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to a microprocessor environment, wherein a plurality of peripheral devices are connected to a microprocessor (CPU), the microprocessor writing data to and reading data from the peripheral devices. To be more specific, the present invention relates to a method circuit arrangement for implementing timing between a microprocessor and its peripheral devices.
2. Description of the Related Art
FIG. 1 shows a hardware environment as described above, wherein four different (having different speeds) peripheral devices A . . . D are connected to a microprocessor 10 by means of its data bus 11 and address bus 12 in a manner known per se. (It should be noted that in the figures presented below, the signal lines are connected to one another only at those points which are indicated by small circles) . In this exemplifying case, the peripheral device A is a medium-speed (one wait state) EPROM, the peripheral device B is a high-speed (no wait states) SRAM (Static Random Access Memory), the peripheral device C is a low-speed (two wait states) peripheral device, and the peripheral device D is a very low-speed (three wait states) peripheral device. It is also assumed that the address hold time of the peripheral device C is two clock cycles, and that the address hold time of the peripheral device D is three clock cycles. (Address hold time will be defined below). The peripheral devices C and D may be for instance serial input-output controllers or A/D converters.
The wait state mentioned above, which represents the speed of a peripheral device, means that a microprocessor extends the assertion period of signals according to the assertion of a corresponding control signal (if the control signal is not asserted, the microprocessor operates as quickly as it is able to). The control signal is usually referred to as a WAIT signal, and in this exemplifying case, this signal is generated in a decoder 13, wherefrom it is applied to the microprocessor. (In some processors, for instance in processors manufactured by Motorola, a corresponding function is implemented with a signal referred to as ACKNOWLEDGE). In the manner described above, it is thus possible to adjust a microprocessor to wait for slower peripheral devices.
The signals used in FIG. 1 have the meanings represented in the following table. The reference of a signal is formed from its generally used English "name", which is shown in brackets after the reference.


______________________________________ Signal Definition ______________________________________ OE (Output Enable) Opens the data bus buffer of a peripheral device in order for the peripheral device to be able to feed data to the data bus WE (Write Enable) A signal which enables data to be written to a peripheral device CE (Chip Enable) A peripheral device selection signal by which one peripheral device at a time is se1ected to be active ______________________________________
In addition, FIG. 1 shows a clock signal CLK and a WAIT signal, and a control signal STB, the meaning of which will be explained below.
Signals OE are occasionally also referred to by an alternative abbreviation RD (i.e. Read; the microprocessor reads from a peripheral device), and signals WE, correspondingly, by an abbreviation WR (i.e. Write; the microprocessor writes to a peripheral device). When a signal WE is valid, desired data must appear in the inputs of the input register of the peripheral device, and when the signal WE is negated, the desired data remains in the peripheral device (i.e. the new data visible in the inputs is no longer able to be written to the peripheral device).
Selection signals CE are typically generated by combination logic in the decoder 13 from the address appearing over the address bus 11, i.e. the signals CE are activated according to the address appearing over the address bus. A certain address range thus corresponds to each peripheral device in such a manner that when the address is located i

REFERENCES:
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patent: 4303990 (1981-12-01), Seipp
patent: 4440986 (1984-04-01), Thorson
patent: 4547630 (1985-10-01), Giammarrusco
patent: 5222226 (1993-06-01), Yamaguchi et al.
Anderson et al: "Two-Speed Control Storage", IBM Technical Disclosure Bulletin, vol. 22, No. 10, Mar. 1980, pp. 4690-4691.

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