Implementation of integrated status of a protection register...

Details Implementation of integrated status of a protection register... Implementation of integrated status of a protection register...

2011-02-15

2011-02-15

Shah, Sanjiv (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S151000, C711S152000, C710S028000, C710S036000, C710S200000, C714S763000

Reexamination Certificate

active

07890721

ABSTRACT:
A protection register array in which the lock status of the protection register is stored outside of the array. An initial verify function is used to read lock status.

REFERENCES:
patent: 5771348 (1998-06-01), Kubatzki et al.
patent: 5873112 (1999-02-01), Norman
patent: 6034889 (2000-03-01), Mani et al.
patent: 6256715 (2001-07-01), Hansen
patent: 6349057 (2002-02-01), Hotaka
patent: 6778443 (2004-08-01), Shiga et al.
patent: 2004/0083346 (2004-04-01), Chevallier et al.
patent: 2004/0141379 (2004-07-01), La Malfa et al.
patent: 2004/0151026 (2004-08-01), Naso et al.
patent: 2004/0205314 (2004-10-01), Babudri et al.
patent: 2005/0024954 (2005-02-01), Dalvi et al.
patent: 2006/0155947 (2006-07-01), DeCaro
Atmel Publication, AT49SN12804, AT49SV12804, “128-megabit (8M x16) Burst/Page Mode 1.8 volt Flash Memory”, Rev. 3314A-Flash, Apr. 2004, 41 pages.

Affiliated with

Also associated with

Rating

Implementation of integrated status of a protection register... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Implementation of integrated status of a protection register..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Implementation of integrated status of a protection register... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2629906