Implementation of configurable on-chip fast memory using the dat

Details Implementation of configurable on-chip fast memory using the dat Implementation of configurable on-chip fast memory using the dat

1998-05-05

2000-07-18

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

711133, 711159, 711134, 711141, 711142, 711163, G06F 1216

Patent

active

060921595

ABSTRACT:
A write-through data cache which incorporates a line addressable locking mechanism. By executing a software lock instruction or unlock instruction, a microprocessor controls the locking or unlocking of individual cache lines in the data cache. A locked cache line is not subject to deallocation. By locking a plurality of lines in the data cache, the microprocessor configures a reserved area of guaranteed fast access memory within the data cache. The data cache includes a mechanism to disable write-through of write requests on a line addressable basis. By executing a software write-through disable instruction, the microprocessor commands the data cache to disable write through operations on an individual cache line. By disabling write-through on cache lines which have been locked, the plurality of locked lines behaves like a true fast-access internal memory with guaranteed access time: write requests targeting the reserved area of locked lines are not written through to the bus interface.

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Stiliadis et al., "Selective Victim Caching: A Method to Improve the Performance of Direct-Mapped Caches," Proceedings of the 27th Annual Hawaii International Conference on System Sciences, 1994, pp. 412-421.

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