Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2006-12-15
2009-06-23
Le, Thong Q (Department: 2827)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S196000, C365S189050, C365S205000, C365S189070
Reexamination Certificate
active
07551498
ABSTRACT:
A redundant memory array has r columns of redundant memory cells, r redundant senses, and a redundant column decoder. Redundant address registers store addresses of defective regular memory cells. Redundant latches are provided in n groups of r latches. Redundancy comparison logic compares addresses of defective regular memory cells with an external input address. If the comparison is true, what is provided is: a DISABLE_LOAD signal to disable the regular senses for one of the n groups of m columns, an ENABLE_LATCH signal to one of the n groups of m columns to disables corresponding regular senses, and one or r REDO signals to a respective one of the r redundant latches in one of the n groups that is disabled. The selected one of the redundant latches activates one of the r redundant senses to access a redundant column.
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“International Application Serial No. PCT/US2007/084460, Search Report mailed Nov. 10, 2008”, 3 pgs.
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Bartoli Simone
Mostola Maria
Sacco Andrea
Surico Stefano
Atmel Corporation
Le Thong Q
Schwegman Lundberg & Woessner, P.A.
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