Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2002-05-13
2004-10-26
Yoha, Connie C. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S212000, C365S149000, C365S189070
Reexamination Certificate
active
06809978
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductor integrated circuits in general and semiconductor integrated memory chips in particular.
2. Discussion of Related Art
A known semiconductor integrated circuit, such as a semiconductor integrated memory IC
100
that is a writeable memory of the DRAM type, is shown in FIG.
1
. Such a dynamic random access memory (DRAM) chip
100
includes a plurality of memory storage cells
102
in which each cell
102
has a transistor
104
and an intrinsic capacitor
106
as shown in FIG.
4
. The memory storage cells
102
are arranged in arrays
108
as shown in
FIGS. 2 and 3
, wherein the memory storage cells
102
in each array
108
are interconnected to one another via columns of conductors
110
and rows of conductors
112
. The transistors
104
are used to charge and discharge the capacitors
106
to certain voltage levels. The capacitors
106
then store the voltages as binary bits, 1 or 0, representative of the voltage levels. The binary 1 is referred to as a “high” and the binary 0 is referred to as a “low.” The voltage value of the information stored in the capacitor
106
of a corresponding memory storage cell
102
is called the logic state of the memory storage cell
102
.
As shown in
FIGS. 1 and 2
, the memory chip
100
includes six address input contact pins A
0
, A
1
, A
2
, A
3
, A
4
, A
5
along its edges that are used for both the row and column addresses of the memory storage cells
102
. The row address strobe (RAS) input pin receives a signal RAS that clocks the address present on the DRAM address pins A
0
to A
5
into the row address latches
114
. Similarly, a column address strobe (CAS) input pin receives a signal CAS that clocks the address present on the DRAM address pins A
0
to A
5
into the column address latches
116
. The memory chip
100
has a data pin Din that receives data and a data pin Dout that sends data out of the memory chip
100
. The memory chip
100
has a pin Vss that receives an external voltage of 5 V. The modes of operation of the memory chip
100
, such as Read, Write and Refresh, are well known and so there is no need to discuss them for the purpose of describing the present invention.
A variation of a semiconductor integrated circuit or a DRAM chip is shown in
FIGS. 5 and 6
. In particular, by adding a synchronous interface between the basic core DRAM operation/circuitry of a second generation DRAM and the control coming from off-chip, a synchronous dynamic random access memory (SDRAM) chip
200
is formed. The SDRAM chip
200
includes a bank of memory arrays
208
wherein each array
208
includes memory storage cells
210
interconnected to one another via columns and rows of conductors.
As shown in
FIGS. 5 and 6
, the memory chip
200
includes twelve address input contact pins A
0
-A
11
that are used for both the row and column addresses of the memory storage cells of the bank of memory arrays
208
. The row address strobe (RAS) input pin receives a signal RAS that clocks the address present on the DRAM address pins A
0
to A
11
into the bank of row address latches
214
. Similarly, a column address strobe (CAS) input pin receives a signal CAS that clocks the address present on the DRAM address pins A
0
to A
11
into the bank of column address latches
216
. The memory chip
200
has data input/output pins DQ
0
-
15
that receive and send input signals and output signals. The input signals are relayed from the pins DQ
0
-
15
to a data input register
218
and then to a DQM processing component
220
that includes DQM mask logic and write drivers for storing the input data in the bank of memory arrays
208
. The output signals are received from a data output register
222
that received the signals from the DQM processing component
220
that includes read data latches for reading the output data out of the bank of memory arrays
208
. The memory chip
200
has a pin Vss that is approximately at ground and a pin V
DD
that receives an external voltage of 3.3 V. The modes of operation of the memory chip
200
, such as Read, Write and Refresh, are well known and so there is no need to discuss them for the purpose of describing the present invention.
A variation of the SDRAM memory chip
200
discussed above is a so-called DDR DRAM memory chip that registers commands and operations on the rising edge of the clock signal while data is transferred on both rising and falling edges of the clock signal. In such a DDR DRAM memory chip, the external voltage received by pin V
DD
is approximately 2.5V.
It is noted that new generations of DRAM, SDRAM and DDR DRAM chips are being designed where the magnitude of the externally and internally generated voltages are being reduced so that power and heat are reduced. With the reduction in the externally generated voltages, there is a need to maintain the internal voltages at their present levels as current loads change and thus increase reliance on such internally generated voltages. With such increased reliance on internally generated voltages, the deleterious effect, on the internally generated voltages based on the temperature of and the effect of the heat of the memory chip due to such factors as current flow and environment, increases.
SUMMARY OF THE INVENTION
One aspect of the present invention regards a voltage control system for an integrated circuit that includes an integrated circuit having an internal voltage generator and a network and a temperature sensor that is positioned so as to sense a temperature of the integrated circuit and generates a signal representative of the sensed temperature. A comparator connected to the temperature sensor and the network so as to receive the signal representative of the sensed temperature and a voltage of the network, wherein the comparator generates a regulating signal that is used to regulate a voltage of the internal voltage generator. A control system is connected to the integrated circuit and the comparator, wherein the control system receives the regulating signal and regulates the voltage of the internal voltage generator based on the regulating signal.
A second aspect of the present invention regards a method of regulating a voltage of an internal voltage generator of an integrated circuit that includes sensing a temperature of an integrated circuit, comparing the sensed temperature with a voltage of a network of the integrated circuit and regulating a voltage of an internal voltage generator of the integrated circuit based on the comparing.
Each of the above aspects of the present invention provides the advantage of compensating the voltages of internal voltage generators of a memory chip for temperature.
Each of the above aspects of the present invention provides the advantage of allowing external voltages supplied to an integrated circuit to be reduced and preventing a substantial decrease in current due to such reduction of external voltages.
The present invention, together with attendant objects and advantages, will be best understood with reference to the detailed description below in connection with the attached drawings.
REFERENCES:
patent: 5278796 (1994-01-01), Tillinghast et al.
patent: 5784328 (1998-07-01), Irrinki et al.
patent: 5873053 (1999-02-01), Pricer et al.
patent: 5994752 (1999-11-01), Sander et al.
patent: 6255892 (2001-07-01), Gartner et al.
patent: 6373768 (2002-04-01), Woo et al.
patent: 6453218 (2002-09-01), Vergis
patent: 6504697 (2003-01-01), Hille
patent: 0314084 (1994-12-01), None
U.S. patent application Ser. No. 10/144,572, Partsch et al., filed May 13, 2002.
U.S. patent application Ser. No. 10/144,579, Edmonds et al., filed May 13, 2002.
Alexander George William
Baker Steven Michael
Brinks Hofer Gilson & Lione
Yoha Connie C.
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