Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-07-22
2004-07-20
Thomas, Tom (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C257S318000, C257S298000, C257S300000
Reexamination Certificate
active
06765257
ABSTRACT:
BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates to integrated circuit structures and fabrication methods, and especially to the fabrication of non-volatile FLASH memory arrays.
Background: FLASH EPROM Layout
FLASH memory (also known as FLASH EPROM or FLASH EEPROM) is an array of transistors which have floating gates. The arrays can be written cell by cell, but are erased as blocks of cells or as an entire array.
Referring to
FIG. 7
, a sample array of memory cells, which is an integral part of a memory chip, is shown. Each cell is a floating-gate transistor
10
having a source
11
, a drain
12
, a floating gate
13
, and a control gate
14
. Each of the control gates
14
in a row of cells
10
is connected to a wordline
15
, and each of the wordlines
15
is connected to a wordline decoder
16
. Each of the sources
11
in a row of cells
10
is connected to a source line
17
. Each of the drains
12
in a column of cells
10
is connected to a drain-column line
18
. Each of the source lines
17
is connected by a common-column line
17
a
to a column decoder
19
and each of the drain-column lines
18
is connected to the column decoder
19
. Further discussion of the array can be found in U.S. Pat. No. 5,659,500, which is hereby incorporated by reference.
As dimensions are scaled down in all areas of integrated circuits, the trend in FLASH arrays has been to eliminate as many source/drain contact points as possible, thus avoiding the extra space needed for these structures. A typical FLASH array layout is shown in FIG.
8
. Here there are drain contacts
34
′ for each transistor
10
, while a single source contact
32
′ is made to serve many cells (e.g. 32). As shown in this figure, LOCOS or field isolations
30
′ are not continuous for older generations with bigger cells, but at 0.5 micron and below, the LOCOS isolations are continuous. In the latter situation, the thermally grown oxide is removed along the horizontal source-line
17
′, by etching, then dopants are implanted and annealed in a self-aligned source (SAS) process, providing the conduction necessary between the source contact and the individual cells.
Vertical source lines
17
A′ cross the horizontal source lines at the source contact
32
′ and are electrically connected to the contact
32
′ through metal leads and not through the moat under the stack since the diffused source implants might not reach through under the stack. Note that the stacks are designed to “bend” around the locations where a source contact is planned, to accommodate the large area needed for the source contact.
Beside the larger space needed, bent stacks cause various problems. The horizontal spacing between field oxide regions is non-uniform (it has to be wider at the vertical source lines than the horizontal spacing in the groups of columns of cells), causing distortion around the vertical source lines. In some cases, the distortion is sufficient that dummy columns of cells are used on each side of the metal vertical source line, resulting in an even larger non-functional area.
Background: In-Line Contacts
In U.S. Pat. No. 5,659,500, it was proposed that the source contacts
32
be moved to the other side of the control gate line
15
to be in line with drain contacts
34
as shown in FIG.
4
.
FIG. 5
, showing cross section A-A′ of
FIG. 4
, reflects the diffusion of dopants from both sides of the stack. This diffusion method shows a good conduction path under the stack, to connect the horizontal sourceline to the contact on the vertical source line, for 0.7 micron stack width where there are no boron implants on the source-lines. In these conditions, phosphorus can diffuse from both side (more than half-way), making a conductive path under the stack. Since the stack width is 0.7 micron, even if the source junction diffusion is more than half way in the channel, there is still about 0.3 micron effective channel length (Leff) left to prevent punch-through in the Floating Gate, Avalanche-injection MOS (FAMOS) cell. But as the stack gets smaller (0.4-0.5 micron), in order to keep a reasonable Leff, the source junction needs to be pulled back so that the above approach may not work. For 0.4 micron stack, the diffusion junctions may not give a good conductive path, a simulation of which is shown in FIG.
6
.
Disclosed Structures and Methods
The present application discloses that, when moving source contacts in line with drain contacts, rather than counting on source diffusions to achieve a good conductive path, an extra arsenic implant can be done right after the poly1 slot etch and before ashing the resist, to place the arsenic under the soon-to-be-deposited control line. The mask for the poly1 slot etch can be slightly modified, so that the etch also removes poly1 at the point where the control gate line will cross the vertical source line, eliminating the need for an additional mask.
FIG. 1
shows a layout similar to
FIG. 4
, with the additional implant shown at
40
.
FIG. 2
shows a cross-section along B-B′ in
FIG. 1
, showing how the disclosed arsenic implantation ensures good conduction under the to connect the vertical and horizontal source lines.
Advantages of the disclosed methods and structures include:
requires less area (about 2% less);
straight stacks are more manufacturable;
straight stacks are more scalable;
no dummy columns are needed around the vertical source lines; and
this approach is independent of line width.
REFERENCES:
patent: 5047814 (1991-09-01), Hazani
patent: 5552738 (1996-09-01), Ko
patent: 5557569 (1996-09-01), Smayling et al.
patent: 5659500 (1997-08-01), Mehrad
Mehrad Freidoon
Picone Kyle A.
Brady III Wade James
Fenty Jesse A
Thomas Tom
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