Implanted asymmetric doped polysilicon gate FinFET

Details Implanted asymmetric doped polysilicon gate FinFET Implanted asymmetric doped polysilicon gate FinFET

2006-06-20

2006-06-20

Lindsay, Jr., Walter L. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S217000, C438S286000

Reexamination Certificate

active

07064019

ABSTRACT:
An asymmetric field effect transistor (FET) that has a threshold voltage that is compatible with current CMOS circuit designs and a low resistive gate electrode is provided. Specifically, the asymmetric FET includes a p-type gate portion and an n-type gate portion on a vertical semiconductor body; an interconnect between the p-type gate portion and the n-type gate portion; and a planarizing structure above the interconnect.

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