Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2006-08-08
2006-08-08
Ghyka, Alexander (Department: 2812)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S530000
Reexamination Certificate
active
07087507
ABSTRACT:
A structure and method passivates dangling silicon bonds by the introduction of deuterium into a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) by ion implantation. The process of implantation provides precise placement of deuterium at optimum locations within the gate stack to create stable silicon-deuterium bond terminations at the Si—SiO2interface within the gate-channel region. The deuterium is encapsulated in the MOSFET by the use of a Silicon Nitride (SiN) barrier mask. The ability of deuterium to passivate dangling silicon bonds is maximized by removing hydrogen present in the MOSFET and by use of an absorption layer to create a deuterium rich region.
REFERENCES:
patent: 5872387 (1999-02-01), Lyding et al.
patent: 5972765 (1999-10-01), Clark et al.
patent: 6114734 (2000-09-01), Eklund
patent: 6143632 (2000-11-01), Ishida et al.
patent: 6147014 (2000-11-01), Lyding et al.
patent: 6943126 (2005-09-01), Narayanan et al.
patent: 2002/0031920 (2002-03-01), Lyding et al.
patent: 2002/0168841 (2002-11-01), Chetlur et al.
patent: 2003/0219950 (2003-11-01), Lyding et al.
patent: WO-94/19829 (1994-09-01), None
patent: WO-97/26676 (1997-07-01), None
J.W. Lyding, K. Hess, and I.C. Kizilyalli, “Reduction of Hot Electron Degradation in Metal Oxide Semiconductor Transistors by Deuterium Processing,” vol. 68, No. 18,Appl. Phys. Lett., pp. 2526-2528, 1996.
W.F. Clark, T.G. Ference, S.W. Millt, J.S. Burnham, and E.D. Adams, “Improved Hot Electron Reliability High-Performance, Multi-Metal CMOS Using Deuterated Barrier-Nitride Processing,”IEEE Electron Device Lett., vol. EDL-20, No. 10, pp. 501-503, 1998.
I.C. Kizilyalli, et al., “Multi-Level Metal CMOS Manufacturing with Deuterium for Improved Hot Carrier Reliability,”IEDM Tech. Dig., pp. 935-937, 1988.
W.F. Clark, P.E. Cottrell, T.G. Ference, S.-H. Lo, J.G. Massey, S.W. Millt, and J.H. Rankin, “Channel Hot Electron and Hot-Hole Improvement in A1 and Cu Multilevel Metal CMOS Using Deuterated Anneals and Passivating Films,”IEDM Tech. Dig., pp. 1999.
I.C. Kizilyalli, J.W. Lyding and K. Hess, “Deuterium Post-Metal Annealing of MOSFET's for Improved Hot Carrier Reliability,”IEEE Electron Device Lett., vol. EDL-18, No. 3, pp. 81-83, 1997.
J. Lee, et al., “The Effect of Deuterium Passivation at Different Steps of CMOS Processing on Lifetime Improvements of CMOS Transistors,”IEEE Trans. Electron Devices, vol. ED-46, No. 8, pp. 1812-1813, 1999.
S. Wolf and R.N. Tauber, “Silicon Processing for the VLSI Era,” vol. 1-3,Lattice Press, 1986-1995.
K. Saadatmand, E. McIntyre, S. Roberge, W. Zhimin, K. Wenzel, R. Rathmell, and J. Dykstra, “Radiation emission for ion implanters when implanting hydrogen and deuterium,”International Conference on Ion Implantation Technology Proceedings, Edited by J. Matsuo, G. Takaoka, and I. Yamada, vol. 1, pp. 292-295, 1998.
D. Misra and R.K. Jarwal, “Reliability of Thin Oxides Grown on Deuterium Implanted Silicon Substrates,”IEEE Trans. Electron Devices, vol. ED-48, No. 5, pp. 1015-1015, 20001.
K. Cheng, K. Hess, and J. W. Lyding, “Deuterium Passivation of Interface Traps in MOS Devices,”IEEE Electron Device Lett., vol. EDL-22, No. 9 pp. 441-443, 2001.
P. J. Chen and R. M. Wallace, “Deuterium Transport Through Device Structures,”Journal of Applied Physics, vol. 86, No. 4, pp. 2237-2244, 1999.
B.J. O'Sullivan, P.K, Hurley, C. Leveugle and J. H. Das, “Si(100)-SiO2Interface Properties Following Rapid Thermal Processing,”Journal of Applied Physics, vol. 89, No. 7, pp. 3811-3820, 2001.
P.K. Hurley, B.J. O'Sullivan, F.N. Cubaynes, P.A. Stolk, F.P. Widershoven and J. H. Das, “Examination of Si(111)-SiO2, Si(110)-SiO2Interfacial Properties Following Rapid Thermal Annealing,”Journal of Electrochemical Society, vol. 149, No. 3, pp. G194-G197, 2002.
Babock Jeff
Cheroff George
Koldiaev Viktor
Ghyka Alexander
PDF Solutions, Inc.
Steptoe & Johnson LLP
Winarski Tyson Y.
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