Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2007-03-27
2007-03-27
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S026000
Reexamination Certificate
active
10983723
ABSTRACT:
A semiconductor device is easy for high accuracy impedance matching against differences in impedance of a transmission line and a package wire. A semiconductor chip having external output buffers and a packaging circuit are included. Each external output buffer has a first output portion whose internal impedance is adjusted commonly with other external output buffers in accordance with impedance control data and a second output portion whose internal impedance is adjusted independently of other external output buffers. Both of the first and second output portions are connected in parallel to a common output terminal. Common adjustment by the first output portion can cope with impedance of the transmission line and individual adjustment by the second output portion can cope with a difference of package wires.
REFERENCES:
patent: 6246255 (2001-06-01), Takizawa
patent: 6445245 (2002-09-01), Schultz et al.
patent: 6967500 (2005-11-01), Lin et al.
patent: 05-166931 (1991-12-01), None
A. Marquez, Esq. Juan Carlos
Cho James H.
Fisher Esq. Stanley P.
Reed Smith LLP
Renesas Technology Corp.
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