Impedance matching circuit, high speed semiconductor...

Details Impedance matching circuit, high speed semiconductor... Impedance matching circuit, high speed semiconductor...

1999-05-21

2001-02-13

Nelms, David (Department: 2818)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S086000, C326S087000

Reexamination Certificate

active

06188237

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a high-speed output circuit disposed on a periphery of a semiconductor integrated circuit, the output circuit interfacing between the semiconductor integrated circuit and an external circuitry or a system bus supposed to be connected to the semiconductor integrated circuit. The high-speed output circuit is well suited for a high speed semiconductor integrated circuit, such as an SRAM, composing a computer system. In particular, the present invention relates to a technique of matching the impedance of an output buffer in the output circuit on a large scale integrated circuit (LSI) with the impedance of the external circuitry or the system bus in the computer system.
2. Description of the Prior Art
LSI chips installed in a computer system are connected to a system bus of the computer system through respective output circuits disposed on the periphery of the LSI chips. As the interface circuit, a small signal amplitude interface circuit, for example, a high-speed transistor logic (HSTL) is recently employed. Each of the impedance of the output circuits of the LSI chips and that of the system bus must match with each other, otherwise signals are reflected at the interface to hinder the operation speed of the LSI and prevent the computer system from fully using the intrinsic high-speed performance of the LSI.
It is very important, therefore, to match the impedance of the system bus of the computer system with that of respective output buffers in the output circuits disposed on the LSI chips, which are supposed to be connected to the system bus. Another problem is that the output impedance of semiconductor elements that form the output buffer of the LSI chip varies in response to a change in a system supply voltage, thereby causing an impedance mismatch between the output buffer and the system bus. This raises a necessity of an impedance matching circuit capable of speedily coping with a change in a system supply voltage.
To realize an impedance matching between the output buffer of an LSI chip and a system bus, an effort for standardization of specifications has been conducted by a technology employing an output circuit referred as “a programmable impedance output circuit”. In the methodology employing the programmable impedance output circuit, an external resistor whose value is determined depending on requirements by users is connected between “a ZQ-pin” of the LSI package and a system bus held at a low level supply voltage VSS arranged on the system bus. The LSI chip periodically samples and sets the impedance of the output buffer of the LSI chip to an inverse multiple (for example, ⅕) of the impedance of the external resistor.
Even if a system supply voltage varies, the programmable impedance output circuit is expected always to match the impedance of the LSI chip's output buffer with the specific impedance, thereby securing a high-speed interfacing operation between the LSI chip and the system bus.
FIG. 1
shows an equivalent circuit of the programmable impedance output circuit according to a prior art. The external resistor RQ is equivalently represented as being connected between a ZQ-terminal and the low level voltage source VSS, and the resistance of the external resistor RQ is monitored. Practically, the external resistor RQ is connected between the ZQ-pin of the LSI package and VSS of the system board (the system bus held at the low level supply voltage VSS), which is usually a grounding (GND) level system bus of the system board. The ZQ-terminal and the ZQ-pin is connected by a known internal structure of the LSI package, such as bonding wire or wiring bump. A load circuit
11
comprises, for example, a MOS transistor. A resistance ratio between the output impedance of the load circuit
11
and the external resistor RQ determines a potential VZQ at the ZQ-terminal. The potential VZQ is used to detect the resistance of the external resistor RQ.
FIG. 2
shows an example of the structure of the programmable impedance output circuit of the prior art. An impedance matching circuit
81
consists of an external resistance monitor
822
and an A/D converter (dummy buffer)
86
as shown in FIG.
3
. The dummy buffer
86
has plural MOS transistors, for example, four MOS transistors
1
X,
2
X,
4
X, and
8
X arranged in parallel with one another between a potential VEVAL and the low level voltage source VSS. The MOS transistors
1
X to
8
X have different gate widths (channel widths) “Ws”. More precisely, the gate width W of the MOS transistor
8
X is eight (=2
3
) times wider than that of the MOS transistor
1
X. The gate width W of the MOS transistor
4
X is four (=2
2
) times wider than that of the MOS transistor
1
X. The gate width W of the MOS transistor
2
X is two (=2
1
) times wider than that of the MOS transistor
1
X. Namely, these parallel-connected four MOS transistors provide different on-state resistance R
ON
, and therefore different impedance values respectively.
The programmable impedance output circuit of
FIG. 2
detects the impedance of the external resistor RQ according to the potential VZQ at the ZQ-terminal and separately controls the ON/OFF states of the MOS transistors
1
X to
8
X in synchronization with a sampling clock signal, to match the combined impedance of the MOS transistors
1
X to
8
X with the impedance of the external resistor RQ. Thereafter, the impedance matching circuit
81
matches the combined impedance of the output buffer
82
with the impedance of the external resistor RQ (or an inverse multiple of the impedance of the external resistor RQ).
The load circuit
11
(
FIG. 3
) consists of a MOS transistor Q
1
and resistors R
0
and R
1
. The resistors R
0
and R
1
have fixed value of resistances respectively, and therefore, the potential VZQ at the ZQ-terminal rises as the external resistance RQ becomes larger and drops as the same becomes smaller.
After the MOS transistor Q
1
in the load circuit
11
is turned on, the control circuit
821
sends a set of data consisting of high level “1” and low level “0” as potential values A
0
to A
3
applied to the respective gate electrodes of the MOS transistors
1
X to
8
X. Namely, the control circuit
821
separately turns on and off the MOS transistors
1
X to
8
X to equalize the potential VZQ at the ZQ-terminal to the high potential VEVAL of the dummy buffer
86
. According to the set of data A
0
to A
3
sent from the control circuit
821
, the combined impedance of the dummy buffer
86
is matched with the impedance of the external resistor RQ or an inverse multiple of the impedance of the external resistor RQ.
Unlike a resistor, a MOS transistor shows nonlinear characteristics in its triode (ohmic) regime. A drain voltage (drain-source voltage) V
DS
of the MOS transistor is dependent on a drain current (drain-source current) I
DS
thereof. Namely, a drain voltage V
DS
of each of the MOS transistors
1
X to
8
X varies depending on the value of the external resistor RQ. Even if the control circuit
821
properly sends the set of the data A
0
to A
3
so that the combined impedance determined by the combination of respective sizes, or the respective gate widths Ws of the MOS transistors may correspond to the external resistor RQ, a drain current I
DS
of each of the MOS transistors will deviate from a current flowing through the external resistor RQ if the drain voltage V
DS
changes. On the other hand, the impedance of the output buffer
82
is set based on a fixed drain voltage V
DS
. Accordingly, the programmable impedance output circuit of the prior art is unable to correctly match the impedance of the external resistor RQ with that of the output buffer
82
.
Generally, the programmable impedance output circuit receives a dedicated high level supply voltage VDDQ that is lower than a main high level supply voltage VDD of an LSI chip, to easily realize an impedance matching. The fixed voltage used to define the impedance of the output buffer
82
is usually set t

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