Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2006-12-12
2006-12-12
Cho, James (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S027000, C326S034000
Reexamination Certificate
active
07148720
ABSTRACT:
An impedance matching circuit has comparator, counter, two current sources, semiconductor resistance device, and variable MOS impedance device. The current sources are respectively coupled to an internal impedance device and an external impedance device. The comparator has two input terminals and an output terminal. The input terminals of the comparator are coupled to the internal and external impedance devices. The output terminal of the comparator is coupled to the counter. The variable MOS impedance device is coupled between the counter and the semiconductor impedance, and is controlled by the counter. When the voltages of the internal impedance and the external impedance are not matched, the variable MOS impedance device can provide the compensating impedance by adjusting the counting value of the counter.
REFERENCES:
patent: 6064224 (2000-05-01), Esch et al.
patent: 6448811 (2002-09-01), Narendra et al.
patent: 6525558 (2003-02-01), Kim et al.
patent: 6833729 (2004-12-01), Kim et al.
patent: 6937055 (2005-08-01), Roy et al.
patent: 200306705 (2003-11-01), None
Cho James
Crawford Jason
Jianq Chyun IP Office
Prolific Technology Inc.
LandOfFree
Impedance matching circuit and method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Impedance matching circuit and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Impedance matching circuit and method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3690936