Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2002-03-11
2003-04-22
Le, Don (Department: 2817)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S083000
Reexamination Certificate
active
06552565
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to an impedance matching circuit for facilitating impedance matching between the characteristic impedance of a cable and the input impedance at the input terminal of a receiver for data transmission and, more particularly, to an impedance matching circuit with adjustable resistance for facilitating impedance matching between the characteristic impedance of the cable and the input impedance at the input terminal of a receiver for data transmission even when the characteristic impedance of the cable varies.
2. Description of the Prior Art
FIG. 1
is a schematic diagram showing a data transmission system. In
FIG. 1
, the data transmission system comprises two portions: a transceiver T
X
10
and a receiver R
X
12
, where a cable
14
is interposed between the transceiver T
X
10
and the receiver R
X
12
for communication. In general, a cable has a characteristic impedance Z
&PHgr;
. If the input impedance Z
in
, at the input terminal of the receiver R
X
12
does not match the characteristic impedance Z
101
of the cable
14
, signal reflection may occur which may distort signals. Therefore, the input impedance Z
in
of the receiver R
X
12
must be properly adjusted to match the characteristic impedance Z
101
of the cable
14
, so as to reduce signal reflection and prevent signals from distortion.
FIG. 2A
to
FIG. 2D
are schematic diagrams showing various conventional impedance matching circuits in accordance with the prior art. In
FIG. 2A
, Z
101
denotes the characteristic impedance of a cable
202
, Z
in
denotes the input impedance
206
viewed at the input terminal of the receiver R
X
208
, and R
101
denotes a stable resistor
204
interposed between the input terminal of the receiver R
X
208
and a voltage source V
dd
. Generally, the input impedance Z
in
206
at the input terminal of the receiver R
X
208
is relatively large. More particularly, the resistance of the input impedance Z
in
206
is much larger than that of the stable resistor R
101
204
. Hence, the parallel connection of the stable resistor R
101
204
and the input impedance Z
in
206
results in a resistance value approximately equal to that of the stable resistor R
101
204
. When the resistance of the stable resistor R
101
204
is determined to be equal to that of the characteristic impedance Z
101
of the cable
202
, impedance matching can be achieved.
In
FIG. 2B
, Z
101
denotes the characteristic impedance of the cable
212
, Z
in
denotes the input impedance
216
viewed at the input terminal of the receiver R
X
218
, and R
101
denotes the stable resistor
214
interposed between the input terminal of the receiver R
X
218
and the ground. Generally, the input impedance Z
in
216
at the input terminal of the receiver R
X
218
is relatively large. More particularly, the resistance of the input impedance Z
in
216
is much larger than that of the stable resistor R
101
214
. Hence, the parallel connection of the stable resistor R
101
214
and the input impedance Z
in
216
results in a resistance value approximately equal to that of the stable resistor R
101
214
. When the resistance of the stable resistor R
101
204
is determined to be equal to that of the characteristic impedance Z
101
of the cable
212
, impedance matching can be achieved.
In
FIG. 2C
, Z
101
denotes the characteristic impedance of a cable
222
, and Z
in
denotes the input impedance
226
viewed at the input terminal of the receiver R
X
228
. The input terminal of the receiver R
X
228
is connected to the drain of a p-channel MOSFET (abbreviated as “PMOS” hereinafter)
224
. The source of the PMOS
224
is connected to a voltage source V
dd
, while the gate of the PMOS
224
is connected to the control terminal of a feedback control circuit
225
. A precise resistor R
ext
227
is interposed between the signal terminal of the feedback control circuit
225
and the voltage source V
dd
. R
eff
denotes the equivalent resistance viewed at the drain of the PMOS
224
, therefore the resistance of the precise resistor R
ext
227
is expressed as R
ext
=&agr;·R
eff
, where the value of &agr; is controlled by the feedback control circuit
225
. Generally, the input impedance Z
in
226
at the input terminal of the receiver R
X
228
is relatively large. More particularly, the resistance of the input impedance Z
in
226
is much larger than the equivalent resistance R
eff
viewed at the drain of the PMOS
224
. Hence, the parallel connection of the equivalent resistance R
eff
and the input impedance Z
in
226
results in a resistance value approximately equal to the equivalent resistance R
eff
When the equivalent resistance R
eff
is determined to be equal to that of the characteristic impedance Z
101
of the cable
222
, impedance matching can be achieved.
In
FIG. 2D
, Z
101
denotes the characteristic impedance of a cable
232
, and Z
in
denotes the input impedance
236
viewed at the input terminal of the receiver R
X
238
. The input terminal of the receiver R
X
238
is connected to the drain of an n-channel MOSFET (abbreviated as “NMOS” hereinafter)
234
. The source of the NMOS
234
is connected to the ground, while the gate of the NMOS
234
is connected to the control terminal of a feedback control circuit
235
. A precise resistor R
ext
237
is interposed between the signal terminal of the feedback control circuit
235
and the ground. R
eff
denotes the equivalent resistance viewed at the drain of the NMOS
234
, therefore the resistance of the precise resistor R
ext
237
is expressed as R
ext
=&bgr;·R
eff
where the value of &bgr; is controlled by the feedback control circuit
235
. Generally, the input impedance Z
in
236
at the input terminal of the receiver R
X
238
is relatively large. More particularly, the resistance of the input impedance Z
in
236
is much larger than the equivalent resistance R
eff
viewed at the drain of the NMOS
234
. Hence, the parallel connection of the equivalent resistance R
eff
and the input impedance Z
in
236
results in a resistance value approximately equal to the equivalent resistance R
eff
. When the equivalent resistance R
eff
is determined to be equal to that of the characteristic impedance Z
101
of the cable
232
, impedance matching can be achieved.
From
FIG. 2A
to
FIG. 2D
, the stable resistor R
101
and the precise resistor R
ext
have to change as the characteristic impedance Z
101
of the cable varies. When there are a considerable number of cables, the number of the stable resistors increases as the number of cables increases, resulting in increased fabrication cost and complexity of the impedance matching circuit.
FIG. 3
is a schematic diagram showing another conventional impedance matching circuit in the prior art. In
FIG. 3
, R
cur
denotes a built-in/external bias resistor
302
for providing the transistor mib
304
with the current I
bias
. A current mirror circuit is composed of the transistor mdrz
306
, the transistor mb7
308
, the transistor mdlz
310
, the transistor mdri
312
, the transistor ma7
314
, the transistor mdli
316
and the transistor mib
304
. Since all the gates of the above transistors are connected together, the current in the current mirror is proportional to the bias current I
bias
according to the W/L ratio of the transistors.
The gate voltage V
ref
of both the transistor muri
318
and the transistor mulz
320
is a reference voltage, the potential level of which is &Dgr;V lower than that of the voltage source V
dd
. The transistor muli
322
, the transistor muri
318
, the transistor mulz
320
and the transistor murz
324
are used for level-shifting, that is, making the gate voltage V
ref
of the transistors decrease to a voltage value approximately equal to the threshold voltage and then outputting an output voltage (i.e., as a source follower).
An operational amplifier with an output voltage V
oa
is composed of the transistor mal
326
, the transistor ma2
328
, the transistor ma3
330
,
Chang Horng-Der
Lee Chao-Cheng
Le Don
Realtek Semiconductor Corp.
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