Impedance matching circuit

Electricity: electrical systems and devices – Safety and protection of systems and devices – Impedance insertion

Reexamination Certificate

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C361S118000, C333S124000

Reexamination Certificate

active

06330138

ABSTRACT:

CLAIM OF PRIORITY
This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C. §119 from an application for IMPEDANCE MATCHING CIRCUIT earlier filed in the Korean Industrial Property Office on Jun. 12, 1998 and there duly assigned Serial No. 21901/1998.
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to an impedance matching circuit and, in particular, to a line impedance matching circuit.
2. Related Art
Impedance matching circuits are generally used to efficiently transfer energy at a junction point where electronic circuits having different characteristic impedances are connected to each other. This is accomplished by rendering the impedances seen on either side of the junction point identical. To this end, it is necessary to match line impedances and load impedances of the circuits. When the line impedances are matched, maximum power can be provided from the power supply. Such line impedance matching is necessary not only for a wire terminal but also for a wireless terminal, and the impedances are matched at 50, 75 and 100&OHgr; according to the characteristics of the circuits. With the progress of the electronic and communication technologies, the consumers of electronic communication products demand more qualified services and, in particular, desire to be provided with various services by a single product. To accede to this demand, various electronic circuits having different characteristics have come to be provided in a single communication product. Accordingly, there is a demand for an impedance matching circuit capable of matching impedances which are different for the various kinds of services provided by the product.
The following patents are considered to be representative of the prior art relative to the invention disclosed herein, but are burdened by the disadvantages set forth herein:
U.S. Pat. No. 4,181,824 for a BALANCING IMPEDANCE CIRCUIT issued to Seidel; U.S. Pat. No. 4,189,676 for a SWITCHING SYSTEM UTILIZING FLEXIBLE CIRCUIT WITH TRANSMISSION LINE FOR MATCHED IMPEDANCE CONNECTIONS issued to Arias et al.; U.S. Pat. No. 4,305,043 for a COUPLER HAVING ARBITRARY IMPEDANCE TRANSFORMATION RATIO AND ARBITRARY COUPLING RATIO issued to Ho et al.; U.S. Pat. No. 4,350,958 for an IMPEDANCE MATCHING CIRCUITRY FOR RADIO FREQUENCY SIGNAL POWER AMPLIFIERS issued to Pagnamenta; U.S. Pat. No. 4,455,537 for a MICROWAVE CIRCUIT INTERCONNECT issued to La Prade et al.; U.S. Pat. No. 4,647,871 for an ADAPTIVE IMPEDANCE MISMATCH DETECTOR SYSTEM issued to Turner Jr.; U.S. Pat. No. 4,694,421 for an INTERFACE SYSTEM WHICH SELECTIVELY PROVIDES IMPEDANCE MATCHING BETWEEN A HOST COMPUTER AND A CONTROL CIRCUIT issued to Ogawa; U.S. Pat. No. 4,480,233 for a PLANAR MULTIPLE OSCILLATOR CIRCUIT issued to Juul; U.S. Pat. No. 4,792,920 for an INTERFACE PROVIDING IMPEDANCE MATCHING BY SELECTIVE CONNECTION OF A RESISTOR ARRAY TO A POWER SUPPLY issued to Ogawa; U.S. Pat. No. 4,829,567 for a LINE INTERFACE CIRCUIT issued to Moisin; U.S. Pat. No. 5,023,951 for an OPTICAL RECEIVERS issued to Kahn; U.S. Pat. No. 5,053,910 for a SURGE SUPPRESSOR FOR COAXIAL TRANSMISSION LINE issued to Goldstein; U.S. Pat. No. 5,253,291 for a HYBRID BALANCE AND COMBINATION CODEC FILTER CIRCUIT issued to Naseer et al.; U.S. Pat. No. 5,310,363 for an IMPEDANCE MATCHED REDUCED CROSS TALK ELECTRICAL CONNECTOR SYSTEM issued to Brownell et al.; U.S. Pat. No. 5,506,868 for a MODEM HAVING AN IMPROVED LINE INTERFACE CIRCUIT, IN PARTICULAR FOR A COMPUTER issued to Cox et al.; U.S. Pat. No. 5,717,685 for a TRANSFORMER COUPLER FOR COMMUNICATION OVER VARIOUS LINES issued to Abraham; U.S. Pat. No. 5,726,582 for a CONTROL CIRCUIT FOR KEEPING CONSTANT THE IMPEDANCE OF A TERMINATION NETWORK issued to Hedberg; U.S. Pat. No. 5,745,276 for a UNIVERSAL OPTICAL SIGNAL RECEIVER issued to Ho et al.; U.S. Pat. No. 5,774,026 for a HIGH FREQUENCY IMPEDANCE TRANSFORMER issued to Cunin et al.; U.S. Pat. No. 5,881,129 for a SELF-MONITORING LINE INTERFACE CIRCUIT issued to Chen et al.; and U.S. Pat. No. 5,907,422 for a UNIVERSAL OPTICAL SIGNAL RECEIVER issued to Ho et al.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an impedance matching circuit for matching different impedances in a communications system providing various services.
To achieve the above object, there is provided an impedance matching circuit for a set-top box including a diplexer at a preceding stage having a given output impedance, and a network interface having a given input impedance different from the output impedance of the diplexer. The impedance matching circuit is connected between the diplexer and the network interface, and matches the output impedance of the diplexer to the input impedance of the network interface.
Further, the impedance matching circuit includes: a transformer having a primary coil and a secondary coil connected to the network interface; a first resistor for connecting an output end of the diplexer to an end of the primary coil of the transformer; a second resistor for connecting another output end of the diplexer to another end of the primary coil of the transformer; and a third resistor connected in parallel with the primary coil of the transformer.
Further, the impedance matching circuit includes: a first coil connected between the diplexer and the first resistor; a second coil connected between the diplexer and the second resistor; a first capacitor connected between the first resistor and the primary coil of the transformer for cutting off a DC voltage therebetween; and a second capacitor connected between the second resistor and the primary coil of the transistor for cutting off a DC voltage therebetween. A composite impedance of the first and second coils cancels a composite impedance of the first and second capacitors.
In addition, the impedance matching circuit comprises a surge protection element, connected in parallel with the diplexer, for protecting the impedance matching circuit from a surge voltage output from the diplexer.


REFERENCES:
patent: 3611198 (1971-10-01), Ma
patent: 4181824 (1980-01-01), Seidel
patent: 4189676 (1980-02-01), Arias et al.
patent: 4305043 (1981-12-01), Ho et al.
patent: 4350958 (1982-09-01), Pagnamenta
patent: 4397037 (1983-08-01), Theriault
patent: 4455537 (1984-06-01), La Prade et al.
patent: 4462010 (1984-07-01), Strammello
patent: 4480233 (1984-10-01), Juul
patent: 4647871 (1987-03-01), Turner, Jr.
patent: 4694421 (1987-09-01), Ogawa
patent: 4792920 (1988-12-01), Ogawa
patent: 4829567 (1989-05-01), Moisin
patent: 4864644 (1989-09-01), Takahashi et al.
patent: 5023951 (1991-06-01), Kahn
patent: 5053910 (1991-10-01), Goldstein
patent: 5180999 (1993-01-01), Edwards
patent: 5253291 (1993-10-01), Naseer et al.
patent: 5310363 (1994-05-01), Brownell et al.
patent: 5471178 (1995-11-01), Hickernell
patent: 5506868 (1996-04-01), Cox et al.
patent: 5717685 (1998-02-01), Abraham
patent: 5726582 (1998-03-01), Hedberg
patent: 5732345 (1998-03-01), Vice
patent: 5745276 (1998-04-01), Ho et al.
patent: 5774026 (1998-06-01), Cunin et al.
patent: 5838527 (1998-11-01), Lawrence et al.
patent: 5881129 (1999-03-01), Chen et al.
patent: 5907422 (1999-05-01), Ho et al.
patent: 5910731 (1999-06-01), Polczynski
patent: 5973568 (1999-10-01), Shapiro et al.
patent: 6091966 (2000-07-01), Meadows

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