Impedance-controlled pseudo-open drain output driver circuit...

Details Impedance-controlled pseudo-open drain output driver circuit... Impedance-controlled pseudo-open drain output driver circuit...

2007-10-01

2009-08-25

Tran, Anh Q (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

C326S027000, C326S030000

Reexamination Certificate

active

07579861

ABSTRACT:
An impedance-controlled pseudo-open drain output driver circuit includes: a process, voltage, and temperature (PVT) detector configured to have a delay line receiving a reference clock and detect a state variation of the delay line according to PVT conditions to output detection signals; a select signal generator configured to generate a driving select signal based on the detection signals and an output data; and an output driver configured to drive an output terminal, the output driver including a plurality of pull-up/pull-down driving blocks controlled by the driving select signal, each of the pull-up/pull-down driving blocks including a resistor having an intended impedance.

REFERENCES:
patent: 6256235 (2001-07-01), Lee
patent: 6642742 (2003-11-01), Loyer
patent: 6819157 (2004-11-01), Cao et al.
patent: 7142027 (2006-11-01), Lee et al.
patent: 1020030018742 (2003-03-01), None
patent: 1020040074682 (2004-08-01), None
“A One-Cycle Lock Time Slew-Rate-Controlled Output Driver” by Young-Ho Kwak, et al.;IEEE International Solid-State Circuits Conference 2007;Feb. 14, 2007; Session 22/Digital Circuit Innovations/22.6; pp. 408-409, 611.

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