Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2001-04-30
2002-10-22
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S086000, C326S090000, C327S108000, C327S175000, C710S108000
Reexamination Certificate
active
06469539
ABSTRACT:
BACKGROUND
1. Technical Field
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device having an impedance controlled output circuit that comprises a mechanism for controlling fluctuation in the turn-on impedance of an output driver to obtain a stable output impedance.
2. Discussion of Related Art
Various semiconductor devices such as microcomputers, memories and gate arrays, etc., are integrated within personal computers and other electrical products such as workstations. Typically, such semiconductor devices comprise an input/output (I/O) pin for inputting data transmitted from another device and an output circuit (e.g., output buffer and driver circuit) for outputting data to another device. When the semiconductor device is integrated within an electrical product, the I/O pin is typically connected to a transmission line that comprises printed wiring on a mounting substrate, for example. The transmission line may act as an interface between one or more semiconductor devices for transmitting data. To achieve optimal data transmission over the transmission line, there should be a match between the output impedance of the I/O pin and the impedance of the transmission line.
The wavelength of signals interfaced between semiconductors is becoming increasingly smaller so as to obtain higher operating speeds and minimize signal transfer delay time. As the wavelength decreases, however, exterior noise interference and reflection of an output signal based on an impedance miss matching in an interface terminal become critical factors in signal transmission. Impedance miss matching is caused by various factors such as external noise, a transformation of power voltage, a change of operation temperature and a change of a fabricating process, etc. If impedance miss matching occurs, high-speed transmission of data is difficult and data comprising an output signal outputted from a data-outputting terminal of a semiconductor device may be distorted. When a semiconductor device receives the distorted output signal, various problems may be encountered such as set-up/hold fail or a failure to detect a requisite input level, etc.
To combat these problems, semiconductor memory devices have implemented variable impedance control schemes (having an architecture shown in
FIG. 1
for example) to provide impedance matching. More specifically,
FIG. 1
illustrates a high-level block diagram of a conventional variable impedance control and output circuit (which as explained below is modified to provide a control mechanism in accordance with the present invention). The variable impedance control circuit comprises an impedance detector
10
, an impedance comparator
20
, a counter
30
, a high code selector (HCS)
40
and a ZQ (impedance) driver
50
. The output circuit comprises a data output buffer
60
and an off chip driver
70
as an output driver.
By way of example, in a high-speed transceiver logic (HSTL) interface, the system of
FIG. 1
is typically utilized for impedance control so as to obtain a desired output impedance within approximately several tens of ohms specifications by using one extra pin. More specifically, assuming a HSTL interface is implemented with the impedance control system of
FIG. 1
, an external resistance is coupled to the extra pin of the semiconductor device to provide impedance control so that the semiconductor device can have a desired output impedance value within a specification of about 35-70 ohms. Referring to
FIG. 1
, initially, an exterior resistance RZQ for a matching (which has a resistance value by about five times the impedance value of an external equipment) is connected between an extra pad ZQPAD of the impedance detector
10
and a ground. The impedance ZQ detector
10
, which comprises an architecture as shown in
FIG. 6
, outputs the pad voltage ZQPAD and reference voltage REFIO.
Referring to
FIGS. 1 and 6
, the reference voltage REFIO level is half the output power voltage level (i.e., VDDQ/2). The impedance comparator
20
compares levels of the reference voltage REFIO and the pad voltage ZQPAD, and outputs an up or down control signal UDZQ as its comparison result. The counter
30
performs an up or down counting operation in response to the up or down control signal UDZQ, respectively, and outputs control code CTQx for selectively turning on or turning off a MOS array
12
(
FIG. 6
) comprising a plurality of MOS transistors. In particular, the counter
30
executes a counting operation for increasing or reducing the value of the control code CTQx. Based on the control code CTQx, corresponding MOS transistors within the MOS array
12
are turned on or off, thus the levels of the reference voltage REFIO and the pad voltage ZQPAD become similar. In this case, the levels of the reference voltage REFIO and the pad voltage ZQPAD become similar to a VDDQ/2 level, and a turn-on resistance value of the MOS array
12
and a resistance value of the exterior resistance RZQ become. mutual. The transistors within the off chip driver
70
are turned on, equally to such MOS transistor provided within the MOS array
12
that correspond to the turning-on state, to thereby match the output impedance with the external impedance (e.g., impedance of the interface). In other words, the construction of the MOS array within both the MOS array
12
and the off chip driver
70
is similar so that the same number of transistors within the off chip driver
70
are turned on in the MOS array
12
to obtain impedance matching. The functions of a high code selector
40
, a ZQ driver
50
and a data output buffer
60
are performed based on such construction.
In particular, the high code selector
40
selects one of a plurality of high control codes CTQx in accordance with a procedure to perform impedance matching, and outputs the selected control code as a high control code CTQDx. The ZQ driver
50
generates a driving code CZQx in response to the selected control code CTQDx when the off chip driver
70
is in a high impedance state, and provides the driving code CZQx to the data output buffer
60
. Thus, a renewed driving code CZQx is generated based on a change of the selected control code CTQDx.
The renewed driving code CZQx is applied to the data output buffer
60
. In response, one of a plurality of buffer units within the data output buffer
60
corresponding to the driving code CZQx is enabled. The enabled unit buffer within the data output buffer
60
receives DLATB and DLAT as memory cell data and respectively generates pull-up output data DOUx and pull-down output data DODx, and outputs it to the off chip driver
70
so that the corresponding transistors within the MOS array are turned on. Therefore, the final output data is determined for a signal level by the selected (enabled) transistors within the off chip driver
70
, and is output via an output terminal DQ. At this time, an output impedance value of such output data is similar to the impedance value of the exterior semiconductor device through the above-mentioned impedance control procedure so as to obtain impedance matching. Thus, the output data can be transmitted to an interface line without distortion since impedance matching prevents or mitigates reflection of the output signal.
One problem associated with the above described impedance control system and method, however, is that it can be subject to turn-on impedance vibrations of the off chip driver
70
due to a vibration (or fluctuation) in the value of the high control code CTQDx output from the high code selector
40
during an impedance control operation. This problem will now be described with reference to
FIGS. 2
,
3
and
4
.
FIG. 2
is a detailed block diagram of the high code selector
40
shown in FIG.
1
.
FIG. 3
is a detailed block diagram of a transmission gate comparing circuit of FIG.
2
.
FIG. 4
is a drawing illustrating an example of the code vibration.
Referring to
FIG. 2
, the control code CTQx that is applied to the high code selector
40
comprises 5 bits, with each bit being
F. Chau & Associates LLP
Tan Vibol
Tokar Michael
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