Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2002-12-20
2004-11-09
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S082000, C326S083000, C326S086000, C326S087000, C326S090000, C326S091000
Reexamination Certificate
active
06815979
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an impedance circuit for controlling the impedance of an I/O circuit on a semiconductor integrated circuit.
2. Description of Related Art
It becomes absolutely necessary for high-speed digital circuits to perform high rate, small amplitude signal transmission. To achieve the high rate signal transmission, the impedance of a transmission line must be matched to that of a transmitting/receiving circuit to reduce reflection and to prevent superfluous noise.
Furthermore, the transmission becomes increasingly difficult because of growing variations in transmission characteristics in signal sequences. To compensate for such a situation, dynamically variable impedance is used for the I/O circuit to maintain the transmission characteristics at desirable conditions.
Thus, various I/O specifications have made their current/voltage standards more rigorous to assure high rate transmission.
For this reason, a circuit for controlling the impedance or current/voltage characteristics becomes essential. Furthermore, it becomes increasingly necessary for a single semiconductor integrated circuit to include a circuit with variable impedance or current/voltage characteristics, or to switch the impedance or current/voltage characteristics statically or dynamically.
FIG. 15
is a block diagram showing a configuration of a conventional impedance control circuit disclosed in Japanese patent application laid-open No. 11-234110/1999, for example. In
FIG. 15
, the reference numeral
1
designates an LSI,
2
designates an impedance control circuit, and
3
designates a control circuit. The reference numeral
5
designates an analog comparator, and
6
designates a variable channel width MOS transistor (called “variable width MOS” from now on). Although it is represented as a single MOS transistor in
FIG. 15
, it actually consists of a plurality of MOS transistors connected in parallel, each of which is controlled into conduction or out of conduction. Thus, the total channel width is determined as the sum of the channel widths of all the conducting MOS transistors, making the channel width variable. In the counter
3
, the reference numeral
7
designates a counter, and
8
designates a register. The reference numerals
9
each designate an output circuit, and
10
and
11
each designate a connecting terminal (called “PAD” from now on). The reference numeral
12
designates a reference resistor (called “R
ref
” from now on),
13
designates a reference voltage (called “Cal_Vref” from now on), and
20
designates a power supply voltage (called “V
dd
” from now on).
Next, the operation of the conventional impedance control circuit will be described.
The conventional impedance control circuit controls the resistance of the variable width MOS
6
such that the Cal_Vref
13
becomes equal to the voltage determined by the ratio between the R
ref
12
and the resistance of the variable width MOS
6
as shown in FIG.
15
.
The control circuit
3
includes the counter
7
for varying a number N
code
in sequence at fixed intervals so that the number N
code
satisfies the following relationship.
W
eff
=W
u
×N
code
where W
eff
is the effective width of the variable width MOS
6
, W
u
is a unit of the channel width variation, and the number N
code
designates the number of MOS transistors to be turned on and off.
FIG. 16
is a graph illustrating the operating principle of the conventional impedance control circuit. The potential at the PAD
10
, the connecting point of the variable width MOS
6
with the R
ref
12
, varies with the number N
code
. The output of the analog comparator
5
makes a transition at the point where the potential passes across the reference voltage Cal_Vref
13
.
FIG. 17
is a diagram illustrating an operating timing of the conventional impedance control circuit. The control circuit
3
monitors the output of the analog comparator
5
. When the output of the analog comparator
5
makes a transition, that is, when the divided voltage by the R
ref
12
and the variable width MOS
6
becomes Cal_Vref
13
, the control circuit
3
stores the number N
code
at that time in the register
8
. Thus, all the output circuits
9
takes the same resistance when the number N
code
stored in the register
8
is supplied.
With this configuration, the resistance of all the output circuits
9
of the semiconductor integrated circuit (LSI)
1
is controlled as follows.
R
m
/(
R
ref
+R
m
)=Cal_Vref/
V
dd
(1)
R
m
=R
ref
×Cal_Vref/(
V
dd
−Cal_Vref) (2)
where R
m
is the resistance of the variable width MOS
6
. In the present specification, a symbol representing a voltage is also used as the value of the voltage whose unit is Volt, and a symbol representing a resistor is also used as the value of the resistor whose unit is &OHgr;.
As described above, the conventional impedance control circuit can equalize the impedance of all the output circuits
9
on the semiconductor integrated circuit. However, it has the following restrictions.
(1) It equalizes the impedance using the single reference voltage.
(2) It sets the Cal_Vref
13
at V
dd
/2 when the resistance R
m
of the variable width MOS
6
is equal to the R
ref
12
.
With the foregoing configuration, the conventional impedance control circuit has the following problems.
(1) To control the impedances to different values in the same chip, it must mount the control circuits by the number of the impedances to be controlled.
(2) It must connect considerable number of reference resistors outside the chip. In addition, it can only adjust the impedances to the values corresponding to the reference resistors connected.
(3) It cannot isolate a parasitic resistance from the resistance of the variable width MOS
6
itself.
SUMMARY OF THE INVENTION
The present invention is implemented to solve the foregoing problems. It is therefore an object of the present invention to provide an impedance control circuit enabling a single control circuit to control a plurality of different impedances in the same semiconductor integrated circuit.
Another object of the present invention is to provide an impedance control circuit capable of reducing the number of reference resistors to be connected externally.
Another object of the present invention is to provide an impedance control circuit capable of carrying out optimum control by measuring the total resistance of the variable width MOS plus the additional resistance at a plurality of bias points, and by isolating the contribution of the additional resistance (parasitic resistance or serial resistance) from that of the variable width MOS.
Another object of the present invention is to provide an impedance control circuit that can adjust to any desired values by carrying out calculation using the measured results of the impedance.
Still another object of the present invention is to provide an impedance control circuit with a reduced number of pins by integrating the reference voltage.
According to one aspect of the present invention, there is provided an impedance control circuit including a comparator for comparing one of a plurality of reference voltages with a voltage across a variable resistor, and a control circuit for establishing a plurality of different impedances corresponding to the plurality of reference voltages in response to a signal output from the comparator. It offers an advantage of being able to control the plurality of impedances on the semiconductor integrated circuit using only one control circuit.
REFERENCES:
patent: 5134311 (1992-07-01), Biber et al.
patent: 6087847 (2000-07-01), Mooney et al.
patent: 6094069 (2000-07-01), Magane et al.
patent: 6157206 (2000-12-01), Taylor et al.
patent: 6445170 (2002-09-01), Pangal et al.
patent: 6445245 (2002-09-01), Schultz et al.
patent: 6448811 (2002-09-01), Narendra et al.
patent: 6489837 (2002-12-01), Schultz et al.
Nguyen Khai M.
Tokar Michael
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