Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2002-11-12
2004-05-11
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S086000, C326S090000, C327S108000, C327S112000, C330S009000
Reexamination Certificate
active
06734702
ABSTRACT:
FIELD OF THE INVENTION
The present invention impedance calibration circuit and more specifically to an impedance calibration circuit for a serial ATA (SATA) transmitter.
BACKGROUND OF THE INVENTION
Current computers use parallel ATA hard drives and other peripherals which are connected to the controller by a 40 or 80 wire ribbon cable. This parallel bus interface is reaching its performance limits at data rates of 133 MB/sec. This interface will be replaced by a serial ATA interface which, in addition to having higher data rates, will utilize low voltage signaling. The SATA interface replaces the 80 conductor ribbon cable with a 4 conductor cable. Problems associated with the ribbon cable in blocking air flow within the computer box and folding the cable during assembly are thus eliminated. The data is sent out in a serialized form as a differential signal pair having a 250 mV signal swing which is much less than the 3 or 5 volt signal swing used in parallel ATA interfaces.
The SATA interface will initially have a data rate of 150 MB/sec which requires a speed of 1.5 Gbps for serial data transmission. The second and third generation data rates will be 300 MB/sec and 600 MB/sec, necessitating transmission speeds of 3.0 Gbps and 6.0 Gbps, respectively.
The impedance of the cable that connects the peripheral to the controller can vary with the type of cable used. Furthermore, the input impedance of the receiver circuit in the peripheral may vary among the manufactures of the peripherals. Signal reflection noise becomes a significant problem at the data transmission speeds that are utilized in SATA devices and will become more severe in the next 2 generations of the standard. At lower frequencies the reflection decays within one clock cycle. At the frequencies utilized in SATA, the system does not have enough time to await the decay of the signal reflection noise. Thus the matching of the transmitter and receiver impedance is more critical. The signal reflection noise problem is further exacerbated by the much lower amplitude of the transmitted signal when compared to parallel ATA transmissions.
It is known from U.S. Pat. No. 6,064,244 to use an up/down counter in an impedance matching circuit. In the patent, the impedance matching is for the p-channel pull-up transistors and the n-channel pull-down transistors of a CMOS digital output driver.
SUMMARY OF THE INVENTION
A general object of the invention is to provide a technique for calibrating a SATA transmitter.
This and other objects and features of the invention are attained by a transmitter for a serial ATA (SATA) interface comprising a transmitter circuit having a differential output and an impedance matching circuit. The impedance matching circuit has a pair of resistors, one of the resistors being in series with each of the differential outputs of the transmitter circuit. A pair of resistor arrays, one of the arrays being in parallel with each of the series resistors, each of the arrays having a plurality of selectable resistors. A calibration circuit coupled to the selectable resistors for selecting resistors in each of the arrays which will be coupled in parallel to the respective series resistor.
Another aspect of the invention includes a serial ATA (SATA) system comprising a transmitter circuit having a differential output, each leg of the differential output having a series resistor. First and second resistor arrays are coupled in parallel to a respective one of the series resistors. A transmission line is coupled to an output node of each of the resistor arrays, the transmission lines each having a characteristic impedance. A host receiver having an input impedance is coupled across each of the transmission lines. A calibration circuit is coupled to the selectable resistors for selecting resistors in each of the resistor arrays which will be coupled in parallel to the respective series resistor whereby the output impedance is calibrated to the AC impedance of the transmission lines and the DC input impedance of the host receiver.
A further aspect of the invention is provided by a method of calibrating output impedance of a serial ATA (SATA) transmitter. A resistor is provided in each leg of a differential output of a transmitter, each resistor being coupled to a transmission line having a characteristic impedance. A resistor array is provided in parallel with each of the resistors, each array having a plurality of selectable resistors. One or more resistors is selected from each of the arrays to calibrate the output impedance of the transmitter to match the characteristic impedance of each transmission line with minimum error.
A still further aspect of the invention comprises an offset correction circuit for a comparator. A first multiplexer couples a first input to a comparator between a first signal source and a first reference source. A second multiplexer couples a second input to the comparator between a second signal source and a second reference source. A logic circuit is coupled to an output of the comparator for detecting when a logical output thereof changes from all logical ones to a combination of logical ones and logical zeros and for determining a central point in the combination of logical ones and logical zeros as a point of minimum error.
Yet another aspect of the invention is provided by a method of correcting for offset in a comparator. A first input to the comparator is coupled between a first signal source and a first reference source. A second input to the comparator is coupled between a second signal source and a second reference source. A logical output of the comparator changing from all logical ones to a combination of logical ones and logical zeros; is detected. A central point in the combination of logical ones and logical zeros is determined to be a point of minimum error.
REFERENCES:
patent: 5510727 (1996-04-01), Culmer et al.
patent: 5973490 (1999-10-01), Nauta
patent: 6064224 (2000-05-01), Esch, Jr. et al.
patent: 6307424 (2001-10-01), Lee
patent: 6331786 (2001-12-01), Whitworth et al.
patent: 6417675 (2002-07-01), Johnson
patent: 6448815 (2002-09-01), Talbot et al.
patent: 6507241 (2003-01-01), Ritter
patent: 6624670 (2003-09-01), Payne et al.
Hasunuma Ryu
Ikeoku Takayuki
Namba Kenji
Brady III W. James
Kempler William B.
Tan Vibol
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
LandOfFree
Impedance calibration circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Impedance calibration circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Impedance calibration circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3244225