Impedance buffer and method

Details Impedance buffer and method Impedance buffer and method

2005-05-26

2010-06-29

Barnie, Rexford N (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S034000, C326S082000, C326S083000, C326S086000, C326S087000, C326S090000, C326S091000, C327S073000, C327S077000, C327S344000, C327S513000, C327S530000, C327S538000

Reexamination Certificate

active

07746096

ABSTRACT:
An impedance buffer has a single comparator with a first input and a second input. A first leg has a first pull-up array in series with a reference resistor. The first input of the single comparator is electrically coupled to a node between the first pull up array and the reference resistor. A second leg has a second pull-up array in series with a pull-down array. The second leg is coupled through a switch to the second input of the single comparator.

REFERENCES:
patent: 6064244 (2000-05-01), Wakayama et al.
patent: 6166563 (2000-12-01), Volk et al.
patent: 6307424 (2001-10-01), Lee
patent: 6541996 (2003-04-01), Rosefield et al.
patent: 6573746 (2003-06-01), Kim et al.
patent: 6734702 (2004-05-01), Ikeoku et al.
patent: 6815979 (2004-11-01), Ooshita
patent: 6836143 (2004-12-01), Song
patent: 7038486 (2006-05-01), Aoyama et al.

Affiliated with

Also associated with

Rating

Impedance buffer and method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Impedance buffer and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Impedance buffer and method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4161502