Immediate system management interrupt source with associated rea

Details Immediate system management interrupt source with associated rea Immediate system management interrupt source with associated rea

1994-02-02

1997-09-23

Harvey, Jack B.

395733, G06F 946

Patent

active

056714246

ABSTRACT:
A power management unit that includes a software writable enable register for receiving an SMI enable bit when the generation of an immediate SMI is desired. When the enable bit is set, an SMI flag register causes the assertion of an SMI signal. The power management unit further includes a reason register that is also writable via software command. The reason register is written prior to the setup of the enable bit with a "reason value" indicative of the reason a pending SMI is being requested. The immediate system management interrupt source allows initiating software to indicate the reason it is requesting an SMI, and causes an associated SMI to be asserted with minimal latency. The immediate system management interrupt source further allows the system management interrupt service routine to quickly determine the reason for the immediate SMI, thereby allowing simplified and more efficient SMI service routines and further allowing greater flexibility in programming. As a result, overall performance of the computer system may be improved.

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