Boots – shoes – and leggings
Patent
1988-10-12
1990-07-10
Atkinson, Charles E.
Boots, shoes, and leggings
378901, G06F 1540
Patent
active
049410946
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to an image reconstruction data processing unit for a X-ray tomographic apparatus and the like, which is adapted to process data for reconstructing a tomographic image of an object on the basis of data on the object from various directions.
BACKGROUND TECHNOLOGY
As is well known, the X-ray tomographic apparatus is used for forming a tomographic image of an object in such a manner that a number of projection data are collected by applying X-rays at various angles and the collected data are processed for image reconstruction. The data processing by such X-ray tomographic apparatus basically comprises the steps of preprocessing, reconstruction and postprocessing. In the preprocessing step, logarithmic conversions, predetermined corrections including X-ray intensity correction, beam quality hardening correction, scattering correction and etc., and filtering are performed and in the reconstruction step, the operation of back projections is performed by using the preprocessed projection data thereby forming image data indicative of a tomographic image of an object. The image data thus obtained are corrected by the postprocessing step to a form suitable for them to be stored in a recording medium.
As an apparatus for performing the above data processing steps at high speeds, there is employed a data processing unit comprising a combination of a fast processing unit (hereinafter referred to as "FPU") and one or a plurality of back projection units (hereinafter referred to as "BPU"). The FPU is provided with a main memorY for storing projection data and an operation part for preprocessing the projection data, and the BPU is provided with a computing element and an image memory having addresses each corresponding to each of pixels of a reconstruction image. To increase the image reconstruction speed, it is considered to operate a plurality of such data processing units in parallel relationships with one another but in that case, the following problems arise. That is, the data on the reconstruction image must be a total sum of back projection data obtained by each BPU and further, the reconstruction image data must be postprocessed by a desired FPU so that buses for reception and transmission of the back projection data between the BPUs and between the FPUs and BPUs. Consequently, the structure of the data processing unit becomes complicated.
DISCLOSURE OF THE INVENTION
The object of the present invention is to provide an image reconstruction data processing unit which though simple in structure, can perform a fast data processing by parallel operations of a plurality of FPUs.
The data processing unit of the present invention comprises a plurality of FPUs and a single BPU connected to the formers. The BPU is characterized by the provision of a plurality of back projection execution parts and a single pixel memory in which a total sum of output data from the formers is stored in a back-projected state.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of one embodiment of the present invention;
FIGS. 2A and 2B are views illustrating projection data on an object in two directions, respectively; and
FIGS. 3 and 4 are block diagrams of other embodiments of the present invention.
BEST MODE FOR WORKING THE INVENTION
The present invention will now be described in detail with reference to the accompanying drawings. In FIG. 1, a single BPU 11 is connected to two FPUs 12 and 13 through general purpose buses 16 and 19. The structure of the BPU is as follows: Two back projection execution parts 14 and 15 are provided so as to correspond to the FPUs 12 and 13. The back projection execution part 14 is provided with an address generating part 17 and a data memory 18 connected to the FPU 12 through the general purpose bus 16, and the back projection execution part 15 is provided with an address generating part 20 and a data memory 21 connected to the FPU 13 through the general purpose bus 19. Further, two registers 22 and 23 are provided in correspondence to the tw
REFERENCES:
patent: 4654797 (1987-03-01), Fujita et al.
patent: 4680709 (1987-07-01), Srinivasan et al.
patent: 4803639 (1989-02-01), Steele et al.
Satta Yusuke
Takiura Yasuro
Atkinson Charles E.
Kojima Moonray
Tbui Kim Thanh
Yokogawa Medical Systems, Ltd.
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