Computer graphics processing and selective visual display system – Computer graphics display memory system – Graphic display memory controller
Reexamination Certificate
2000-03-14
2004-02-10
Bella, Matthew C. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Graphic display memory controller
C345S531000, C382S232000
Reexamination Certificate
active
06690378
ABSTRACT:
TECHNICAL FIELD
The present invention relates to an image processing apparatus and an image processing method and, more particularly, to image processing in which input image data is temporarily stored in a storage device, and the stored image data is subjected to coding.
BACKGROUND ART
Although image data including a time-varying image is originally analog data, when this data is digitized, various kinds of complicated signal processing and data compression can be performed on the data and, therefore, the technology of image digitization forms an important field. In an image processing apparatus according to a prior art, input analog image data is subjected to analog-to-digital conversion and compressive coding for recording or transmission, and generally the digitized image data is temporarily stored in a high-speed storage unit such as a memory before being subjected to compressive coding. An example of an image processing apparatus with such temporary storage is disclosed in Japanese Patent Application No. Hei. 7-273461, in which digital image data is temporarily stored in a memory called an image frame memory.
FIG. 10
is a block diagram showing the structure of an image processing apparatus according to the prior art. As shown in the figure, the prior art image processing apparatus is provided with an A/D converter
1001
, an image input controller
1002
, a memory controller
1003
, an encoder
1004
, an input image memory
1005
, and a rate buffer
1006
, and this apparatus receives an analog video signal S
1051
and outputs coded data S
1057
. In
FIG. 10
, signals shown by solid lines indicate the flow of data to be processed, and signals shown by broken lines indicate the flow of signals for control.
The A/D converter
1001
subjects the input analog video signal S
1051
to analog/digital conversion to generate digital image data S
1052
. The image input controller
1002
generates an image input enabling signal S
1061
indicating whether the input digital image data S
1052
is “effective” or “ineffective”. The memory controller
1003
controls storage and readout of the digital image data into/from the memory. The encoder
1004
subjects the digital image data S
1055
to a predetermined compressive coding process to generate coded data S
1056
.
The input image memory
1005
temporarily stores the digital image data S
1054
for the work of the compressive coding process. In the prior art image processing apparatus, the input image memory is divided into plural regions each region storing a predetermined quantity of digital image data. Here, the input image memory
1005
has two regions, namely, a first region
1005
a
and a second region
1005
b
, each region being able to store one frame (one screen) of digital image data.
The rate buffer
1006
temporarily stores the coded data S
1056
generated by the coder
1004
and outputs the data so that the output S
1057
from the image processing apparatus is output at a constant rate. Hereinafter, the operation of the prior art image processing apparatus so constructed will be described.
When an analog video signal S
1051
is input to the image processing apparatus, the analog video signal S
1051
is input to the A/D converter
1001
, wherein it is subjected to analog/digital conversion. The A/D converter
1001
generates digital image data S
1052
and outputs this data to the image input controller
1002
. The input analog video signal S
1051
includes a signal of an effective region corresponding to a portion of image to be displayed, and a signal of an ineffective region other than the effective region. The image input controller
1002
generates an image input enabling signal S
1061
indicating whether the input digital image data S
1052
is “effective” or “ineffective”, and outputs both of the digital image data S
1053
and the image input enabling signal S
1061
to the memory controller
1003
.
The memory controller
1003
stores the digital image data S
1053
in the input image memory
1005
, according to the image input enabling signal S
1061
supplied from the image input controller
1002
and an image input request signal S
1063
supplied from the encoder
1004
which is described later. When the encoder
1004
goes into the coding executable state and outputs an image input request signal S
1063
indicating a request for digital image data to be subjected to coding, to the memory controller
1003
, the memory controller
1003
stores the digital image data S
1053
in the first region
1005
a
of the input image memory according to the image input enabling signal S
1061
indicating that the digital image data S
1053
is effective.
When a predetermined amount of the digital image data S
1053
is stored in the first region
1005
a, the memory controller
1003
generates a coding start signal S
1062
and outputs it to the encoder
1004
so that the encoder
1004
starts coding. Here, the memory controller
1003
generates the signal when one frame of digital image data has been stored.
The encoder
1004
does not perform coding until it receives the coding start signal S
1062
directing coding, from the memory controller
1003
. When the encoder
1004
has received this signal, it receives the digital image data S
1055
stored in the first region
1005
a
through the memory controller
1003
, and performs coding of this data. This coding is carried out according to a predetermined scheme. For example, one frame of digital image data is divided into plural blocks each having a predetermined size, and coding is carried out block by block. When this coding is carried out, the size of each block is generally 8×8 pixels or 16×16 pixels. Further, “a pixel” is discrete unit data as a component of digital image data, and it has a pixel value showing the brightness or color of the image.
The encoder
1004
outputs coded data S
1056
generated by the coding, to the rate buffer
1006
. The coded data S
1056
, which has temporarily been stored in the rate buffer
1006
, is output to the outside of the image processing apparatus as an output S
1057
from the apparatus, for transmission or the like. On the other hand, as the coding is executed, the encoder
1004
generates an image input request signal S
1063
indicating that one frame of digital image data to be coded next is to be input, and outputs this signal S
1063
to the memory controller
1003
.
In the memory controller
1003
, the digital image data S
1053
is stored in the input image memory
1005
according to the image input request signal S
1063
and the input enabling signal S
1061
indicating that the digital image data S
1053
is effective. As described above, one frame of digital image data is stored in the memory
1005
. However, at this time, the memory controller
1003
stores the data in the second region
1005
b
different from the first region
1005
a.
When one frame of digital image data S
1053
(a unit of digital image data) has been stored in the second region
1005
b
, the memory controller
1003
generates a coding start signal S
1062
indicating that coding should be started, and outputs this signal to the encoder
1004
. If the encoder
1004
has ended coding of the previous one frame of digital image data (data which were stored in the region
1005
a
) when it receives the coding start signal S
1062
which directs the encoder to start coding, from the memory controller
1003
, the encoder
1004
receives the digital image data S
1055
stored in the second region
1005
b
through the memory controller
1003
, performs coding of this data, and outputs coded data to the rate buffer
1006
.
As described above, in the prior art image processing apparatus, digital image data is stored alternately in the first region
1005
a
and the second region
1005
b
possessed by the input image memory
1005
, and the stored data is read alternately from these regions to be coded by the encoder
1004
.
FIG. 11
is a timing chart showing the processing status in the normal state wherein the above-mentioned processing is carried out normally. In
FIG. 11
Fujimoto Hitoshi
Kohashi Yasuo
Kuromaru Shunichi
Tojima Masayoshi
Bella Matthew C.
Matsushita Electric - Industrial Co., Ltd.
Monestime Mackly
Wenderoth , Lind & Ponack, L.L.P.
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