Computer graphics processing and selective visual display system – Computer graphics display memory system
Reexamination Certificate
2005-05-10
2005-05-10
Bella, Matthew C. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphics display memory system
C345S519000, C382S276000
Reexamination Certificate
active
06891542
ABSTRACT:
An image processing integrated circuit including a CPU configured to supply an image data, frame information of the image data and a first write destination address indicating an address to which the image data is written; a latch circuit configured to receive the frame information from the CPU; an address scrambler configured to allocate second write destination addresses based on the first write destination address supplied from the CPU and the frame information supplied from the latch circuit; a RAM configured to store the image data supplied from the CPU according to the second write destination address supplied from the address scrambler; and a DA converter configured to perform the digital-analog conversion for the image data supplied from the RAM and for supplying a first read destination address corresponding to the first write destination address one to one, to the address scrambler after the conversion.
REFERENCES:
patent: 5528361 (1996-06-01), Sakata
patent: 6172918 (2001-01-01), Hidaka
patent: 6282310 (2001-08-01), Kadowaki
patent: 11-15962 (1999-01-01), None
Kaneko Yoshio
Yoshida Shigeki
Bella Matthew C.
Kabushiki Kaisha Toshiba
Monestime Mackly
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