Computer graphics processing and selective visual display system – Computer graphics display memory system – Texture memory
Reexamination Certificate
1999-03-02
2004-10-12
Razavi, Michael (Department: 2672)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Texture memory
C345S531000
Reexamination Certificate
active
06803918
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a graphic drawing image processing apparatus, and more particularly to a technical field of storing texture data to be applied to a graphic element to be drawn in a built-in memory when a DRAM or other memory and a logic circuit are provided together.
2. Description of the Related Art
Computer graphics are often used in a variety of computer aided design (CAD) systems and amusement machines. Especially, along with the recent advances in image processing techniques, systems using three-dimensional computer graphics are becoming rapidly widespread.
In three-dimensional computer graphics, the color value of each pixel is calculated at the time of deciding the color of each corresponding pixel. Then, rendering is performed for writing the calculated value of the pixel to an address of a display buffer (frame buffer) corresponding to the pixel.
One of the rendering methods is polygon rendering. In this method, a three-dimensional model is expressed as a composite of triangular unit graphics (polygons). By drawing the polygons as units, the colors of the display screen are decided.
In polygon rendering, coordinates (x, y, z), color data (R, G, B,), homogeneous coordinates (s, t) of texture data indicating a composite image pattern, and a value of the homogeneous term q for the respective vertexes of the triangle in a physical coordinate system are input and processing is performed for interpolation of these values inside the triangle.
Here, the homogeneous term q is simply stated, like an expansion or reduction rate. Coordinates in a UV coordinate system of an actual texture buffer, namely, texture coordinate data (u, v) are comprised of the homogeneous coordinates (s, t) divided by the homogeneous term q to give “s/q” and “t/q” which in turn are multiplied by texture sizes USIZE and VSIZE, respectively.
FIG. 15
is a view of the system configuration showing a basic concept of a three-dimensional computer graphic system.
In this three-dimensional computer graphic system, data of drawing graphics is supplied from a main memory
2
in a main processor
1
or from an input/output (I/O) interface circuit
3
for receiving graphic data from outside via a main bus
4
to a rendering circuit
5
having a rendering processor
5
a
and a frame buffer memory
5
b.
In the rendering processor
5
a
, a frame buffer memory
5
b
for maintaining data for display and a texture memory
6
for maintaining texture data to be applied on the surface of a graphic element (for example, a triangle) to be drawn are connected
Then, the rendering processor
5
a
performs processing for drawing the graphic element applied with the texture on its surface for every graphic element to the frame buffer memory
5
b.
The frame buffer memory
5
b
and the texture memory
6
are generally configured by a DRAM (dynamic random access memory). In the system of
FIG. 15
, the frame buffer memory
5
b
and the texture memory
6
are configured as physically separated memory systems.
Note that, even after it became possible to provide the DRAM and a logic circuit together, to hold the texture data inside has been difficult due to both the limit of the DRAM capacity and the processing speed.
In the so-called built-in DRAM system of the related art above, when the frame buffer memory and the texture memory are provided separately in separate memory systems, there are the disadvantages as stated below:
First, the frame buffer memory which is emptied due to a change of the display resolution cannot be used as a texture memory.
This becomes a big disadvantage when trying to perform all of the processing in the limited capacity of a built-in DRAM.
Second, when making the frame buffer memory and the texture memory physically identical, in simultaneous access to the frame buffer memory and the texture memory, the overhead of switching pages of the DRAM etc. becomes large, so the performance has to be sacrificed.
These disadvantages are not particularly limited to a graphic drawing apparatus of a built-in DRAM type and have been disadvantages in systems of an externally provided DRAM type as well, but have not been as serious as the built-in type where the capacity is strictly limited.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an image processing apparatus capable of performing flexible and high speed processing, wherein a memory region which is emptied due to a change of display resolution can be used as a texture memory, increase of overhead such as switching pages can be prevented, and a reduction of the performance Is not caused.
To achieve the above object, according to a first aspect of the present invention, there is provided an image processing apparatus comprising a memory circuit for storing display data and texture data required by at least one graphic element and a logic circuit for performing processing for applying the texture data on the surface of the graphic element of the display data based on the stored data of the memory circuit, the memory circuit and the logic circuit being both accommodated in one semiconductor chip.
According to a second aspect of the present invention, there is provided an image processing apparatus for performing rendering by receiving polygon rendering data including three-dimensional coordinates (x, y, z). R (red), G (green), and B (blue), homogeneous coordinates (s, t) of a texture, and a homogeneous term q with respect to vertexes of a unit graphic, at least comprising a memory circuit for storing display data and texture data required by at least one graphic element; an interpolation data generation circuit for interpolating the polygon rendering data of vertexes of the unit graphic to generate interpolation data of pixels positioned inside the unit graphic; and a texture processing circuit for dividing the homogeneous coordinates (s, t) of a texture included in the interpolation data by the homogeneous term q to generate “s/q” and “t/q”, using a texture address corresponding to the “s/q” and “t/q” to read texture data from the memory circuit, and applying the texture data on the surface of the graphic element of the display data; the memory circuit, the interpolation data generation circuit, and the texture processing circuit being accommodated in one semiconductor chip.
In the present invention, the memory circuit is divided into a plurality of modules having identical functions; and the logic circuit accesses the modules in parallel.
Further, in the present invention, display elements at adjacent addresses in a display address space are arranged to be different memory blocks in the memory circuit.
Further, in the present invention, indexes in index colors and values of a color look-up table for referring to colors are stored in the memory circuit.
Further, information of a depth of an object to be drawn is stored in the memory circuit.
According to the present invention, by providing a DRAM or other memory circuit and a logic circuit together in one semiconductor chip and by storing display data and texture data required by at least one graphic element in a built-in memory circuit, the texture data can be stored in a portion other than a display region, so the built-in memory can be efficiently used.
Also, by giving identical functions in the memory circuit in parallel as a plurality of independent modules, the efficiency of parallel operations is improved. When the number of bits of the data is simply large, the efficiency of use of data is deteriorated and improvement of the performance is limited to cases of certain conditions, but to Improve the average performance, bit lines can be efficiently used by providing a plurality of modules having certain degrees of functions.
Further efficient usage of the bit lines becomes possible by tinkering with the arrangement of the built-in memory circuit, that is, the address space occupied by the independent memory plus function modules.
When there are frequent accesses to relatively fixed display regions as in drawing g
Horioka Toshio
Ohmori Mutsuhiro
Good-Johnson Motilewa
Kananen Ronald P.
Rader & Fishman & Grauer, PLLC
Razavi Michael
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