Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Patent
1997-07-30
2000-09-26
Cabeca, John W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
711105, 345515, G06F 1202
Patent
active
061254320
ABSTRACT:
Screen data consists of two sets of field data. Each set of field data is divided into a plurality of data blocks which has four rows of pixel data corresponding to four rows of pixels vertically arranged. Every data block corresponding to one set of field data is stored in the first bank (bank0) of a frame buffer memory while that corresponding to the other set of field data is stored in the second bank (bank1). One row address is assigned to each data block. Bank1 is precharged while bank0 is in a write operation and vice versa in order to carry out the precharging operation and the write operation concurrently, so that the pixel data can be transferred at a high data transfer rate and each of two sets of field data can be transferred independently.
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Hanami Atsuo
Ishihara Kazuya
Kumaki Satoshi
Matsumura Tetsuya
Nakagawa Shin-ichi
Cabeca John W.
Chow Christopher S.
Mitsubishi Denki & Kabushiki Kaisha
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