Computer graphics processing and selective visual display system – Computer graphics display memory system – Plural storage devices
Reexamination Certificate
2001-05-31
2004-05-04
Tung, Kee M. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Plural storage devices
C345S560000, C345S556000
Reexamination Certificate
active
06731293
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an image output device and an image output control method.
BACKGROUND OF THE INVENTION
In recent years, portable terminals which uses a liquid crystal display (LCD) have increased in number, and the importance of image display is rising, while the reduction in power consumption has presented a significant challenge. Normally, the liquid crystal display requires a high display refresh rate, and needs 60-Hz updating. However, the image generation is carried out at 30 Hz or lower, so the difference in the rates is absorbed by providing a frame buffer or the like.
Japanese Published Patent Application No. Hei.07-77958 discloses such an electronic plotting device having a frame buffer, which will be described with reference to FIG.
15
.
FIG. 15
is a block diagram illustrating a structure of the electronic plotting device
1
.
In
FIG. 15
, a data supply unit
10
comprises an intermediate data generation unit
11
for generating intermediate data from graphic element data, and a pictographic data generation unit
12
for generating pictographic data from the intermediate data which are generated by the intermediate data generation unit
11
. The data supply unit
10
converts the graphic element data into the pictographic data which are dot data rows in order of the scanning by a visualization device, and supplies the pictographic data to an output selection unit
30
and a cluster control unit
60
. Frame memories
20
and
21
each stores second internal pictographic data which are one frame of the pictographic data supplied by the output selection unit
30
. In accordance with input of a R/W control signal from a control unit
50
, the frame memories
20
and
21
set one of two modes, i.e., a writing mode of writing one frame of the pictographic data and a reading mode of reading the stored one frame of the pictographic data. The output selection unit
30
selects one of first internal pictographic data which are supplied by the data supply unit
10
, third internal pictographic data which are supplied by the frame memories
20
or
21
, and fourth internal pictographic data which are supplied by the cluster control unit
60
. A data display unit
40
displays the output pictographic data which are supplied by the output selection unit
60
. The control unit
50
controls the device in its entirety. The cluster control unit
60
controls plural frames of the pictographic data to confluent successively.
The operation of the so-constructed electronic plotting device
1
will be described.
When a unit timing signal for indicating a position on a time series of the output pictographic data which are supplied to the data display unit
40
is input to the control unit
50
, the control unit
50
generates a local timing signal for the internal processing of the data supply unit
10
and the like. This signal is basically the unit timing signal or the one which is obtained by adjusting the phase of the unit timing signal, and a signal which controls the supply of graphic element data which are required to be controlled to be asynchronous to the local timing signal is further added.
In addition, the control unit
50
generates a plotting section specification signal for specifying one plotting section in one frame, and outputs the signal to the intermediate data generation unit
11
. The intermediate data generation unit
11
refers to the input graphic element data, and outputs intersection coordinates of a pattern border and a plotting line within the specified plotting section to the pictographic data generation unit
12
. The pictographic data generation unit
12
generates the first internal pictographic data.
The first internal pictographic data are input to the output selection unit
30
and the cluster control unit
60
. The cluster control unit
60
polymerizes (composes) the supplied first internal pictographic data and the third internal pictographic data which are supplied by the frame memories
20
or
21
, and output the fourth internal pictographic data to the output selection unit
30
.
The output selection unit
30
selects one of the first internal pictographic data and the fourth internal pictographic data, and outputs selected data to the data display unit
40
, or the frame memories
20
and
21
, or the data display unit
40
as well as the frame memories
20
and
21
. This selection process is carried out in accordance with the output control signal which is supplied by the control unit
50
. The pictographic data which are supplied from the output selection unit
30
to the data display unit
40
are referred to as the output pictographic data, and the pictographic data which are supplied from the output selection unit
30
to the frame memories
20
and
21
are referred to as the second internal pictographic data. Two frame memories
20
and
21
are provided in the prior art, while the frame memories can be more than two.
When the output pictographic data are supplied to the data display unit
40
, the data display unit
40
displays the data, and when the second pictographic data are supplied to the frame memories
20
and
21
, the frame memories
20
and
21
output the third internal pictographic data to the output selection unit
30
and the cluster control unit
60
.
In cases where the first internal pictographic data cannot be output to the data display unit
40
in real time, i.e., the frame rate is low, the first internal pictographic data from the data supply unit
10
are supplied to the frame memories
20
and
21
, and the control unit
50
controls the output selection unit
30
so that the third internal pictographic data which are output from one of the frame memories
20
and
21
are supplied to the data display unit
40
.
In the Institute of Electronics, Information and Communication Engineers (IECE) technological research report, Vol.100, No.42, “Integrated Circuit”, an architecture which outputs data from a single DRAM is disclosed in “A Development of a DMA Controller Unit in a MPEG4 Codec LSI”, and the power consumption of LSI is described in Proc of CICC '99, pp 69-72, May 1999, “A MPEG4 Programmable Codec DSP with an Embedded Pre/Post-processing Engine”. According to these documents, when an image of a CIF (352×288) size is subjected to 15 Hz-codec, the data transfer quantity related to a video interface (VIF) accounts for 41% of the entirety, and the operation ratio of a DMA bus and the operation ratio of the VIF are high. This is described with reference to FIG.
16
.
FIG. 16
is a block diagram illustrating a structure of the MPEG4 codec LSI. This LSI comprises a processor
161
, a video I/O interface
164
, a host interface
160
, and a DMA controller
163
. Image data which are stored in a SDRAM
162
are suited for NTSC format images, and output to an NTSC encoder (DAC)
166
through the VIF
164
by 60 fields per sec. At this time, the power consumed in the entire chip except for the SDRAM
162
is about 640 mW.
Japanese Published Patent Application No. Hei.09-93578 discloses an image transmitter and an image receiver, which can easily convert the resolution of an image to be coded or decoded. In this image transmitter, a frame rate setting register is shown, and in the image receiver, the techniques related to a writing control and a reading control for a frame memory are shown, which are described with reference to
FIGS. 17 and 18
.
In the image transmitter shown in
FIG. 17
, a video signal is digitized by an A/D converter
19
, and a switch is switched for each frame to input the signal to an image frame memory
22
or
23
. A reading/writing control means
21
decides a pixel sampling method on the basis of a signal processing time of a QCIF image which is obtained by dividing an image of CCIR601 level, so as to have a frame rate within the one which is specified by a target frame rate setting means
26
. To be more specific, in order to reduce the resolution of the input image, the CCIR601 level image is down-sampled by the reading/writing control mea
Matsuo Masatoshi
Moriiwa Toshihiro
Tojima Masayoshi
Parkhurst & Wendel L.L.P.
Tung Kee M.
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