Image frame buffer access speedup by providing multiple buffer c

Details Image frame buffer access speedup by providing multiple buffer c Image frame buffer access speedup by providing multiple buffer c

1987-11-16

1992-04-28

Lee, Thomas C.

Boots, shoes, and leggings

364DIG2, 3649207, 3649269, 3649272, 395163, G06F 1562

Patent

active

051095203

ABSTRACT:
A frame buffer memory controller allows rapid image updating while maintaining screen refresh data flow rate. One frame buffer memory controller controls one or more pixel depth columns comprising one or more frame buffer memory chips per pixel. Each frame buffer memory controller listens on a display processor bus for read, write or read-modify-write commands addressed to a pixel, or memory chip, under its control. Such commands, along with the associated addresses and data, are stored in a first-in, first-out (FIFO) buffer for execution during the first free memory cycle.

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patent: 4363104 (1982-12-01), Nussmeier
patent: 4394753 (1983-07-01), Penzel
patent: 4509043 (1985-04-01), Mossaides
patent: 4642794 (1987-02-01), Lavelle et al.

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