Facsimile and static presentation processing – Static presentation processing – Memory
Reexamination Certificate
1999-12-30
2002-10-29
Evans, Arthur G. (Department: 2622)
Facsimile and static presentation processing
Static presentation processing
Memory
C358S001400
Reexamination Certificate
active
06473195
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an image forming apparatus for preventing the delay in transmission of video data to an engine, and to a video data transmitting method therefor.
2. Description of the Related Art
An image forming apparatus such as a printer or a copier forms an image corresponding to received print data on a sheet of paper. A printer receives print data from a computer connected to the printer through a communications interface while the copier receives print data from a scanner scanning an object to be copied.
FIG. 1
is a view showing the structure of a conventional image forming apparatus. Referring to the drawing, the image forming apparatus includes a central processing unit (CPU)
11
, a main frame buffer memory
12
, a direct memory access (DMA) controller
13
, a video data output controller
14
, a video sync signal controller
15
, and an engine
16
.
The CPU
11
converts print data received from the outside to video data suitable for driving the engine
16
and stores the converted video data in the main frame buffer memory
12
.
The engine
16
is configured to print and output an image corresponding to the received video data in a sheet of paper. To enable the engine
16
to begin an image print task using a sheet of paper, each of parts the constituting the engine
16
should be in a ready mode to perform the print task. When receiving a print command from the CPU
11
, the engine
16
requires has each part to be ready to perform the print task. That is, a rotary polygonal mirror or a scan disk (a disk where a holographic pattern for deflecting input light is formed), which are deflection devices in a laser scanning unit, is rotated to set speeds required for performing the print task, a transfer device is heated to a set temperature, or each part is checked whether there is any problem in performing the print task. When the preparation of performing the print task is completed, the engine
16
outputs a print start signal for indicating that it is possible to start the print task to the video sync signal controller
15
.
The DMA controller
13
controls the main frame buffer memory
12
such that the video data stored in the main frame buffer memory
12
can be output to the video data output controller
14
when a print start signal is output from the video sync signal controller
15
from the engine
16
.
The video data output controller
14
temporarily stores the video data received from the main frame buffer memory
12
and outputs the video data to the engine
16
by being controlled by the video sync signal controller
15
.
The video sync signal controller
15
controls the operation of the DMA controller
13
and the time when the video data is output from the video data output controller
14
according to a video data output control signal output from the engine
16
. The video data output control signal output from the engine
16
includes a print start signal, a print stop signal, and a video clock sync signal. The print stop signal is generated from the engine
16
when the video data corresponding to a single page and/or file is completely written to a photoreceptor medium. The video clock sync signal is output from a video clock generator (not shown) provided in the engine
16
for recording of the video data on the photoreceptor medium according to a position a pixel.
The video data output controller
14
outputs the video data to the engine
16
by synchronizing the same with the video clock signal output from the video sync signal controller
15
.
In a method for transmitting video data from the main buffer memory
12
to the video data output controller
14
in the conventional image forming apparatus, as shown in
FIG. 2
, when a print start signal is output from the video sync controller
15
, a main frame buffer memory access controller
13
a
of the DMA controller
13
controls output of video data from the main frame buffer memory
12
so that the video data stored in the main frame buffer memory
12
is transmitted to the video data output controller
14
. When the video data transmitted from the main frame buffer memory
14
completely fills an inner memory, the video data output controller
14
outputs a FF (full flag) signal indicating that the data is full. When the FF signal is input, the main frame buffer memory access controller
13
a
stops transmission of the video data from the main frame buffer memory
12
to the video data output controller
14
. Also, when the stored video data is all output to the engine
16
and no video data is left, the video data output controller
14
outputs an empty signal to the main frame buffer memory access controller
13
a
. Then, the main frame buffer memory access controller
13
a
controls again the transmission of the video data until the video data output controller
14
is completely filled with the video data stored in the main frame buffer memory
12
.
In the above conventional video data transmission method, a delay in time between the point when the video data is received from the main frame buffer memory
12
and the point when the empty signal is output from the video data output controller
14
is generated. As a result, when a high speed printing is performed, the time delay until the video data is received after the video data in the video data output controller
14
is emptied, lowers the entire print time.
SUMMARY OF THE INVENTION
To solve the above problem, it is an objective of the present invention to provide an image forming apparatus which can present a time delay in the transmission of video data to an engine and a video data transmitting method therefor.
Accordingly, to achieve the above objective, there is provided an image forming apparatus which comprises an engine for forming an image corresponding to received video data on a sheet of paper, a main frame buffer memory, an auxiliary frame buffer memory for outputting stored video data along a data transmission path to the engine according to a video clock sync signal, and a first signal when a lower level correspondingly set to at least some amount of the stored video data is reached, and a second signal when the stored data reaches a set upper level. The apparatus further comprises a central processing unit for converting print data received externally to video data suitable for driving of the engine and storing the converted video data in the main frame buffer memory and a direct memory access controller for controlling the main frame buffer memory so that video data stored in the main frame buffer memory is transmitted to the auxiliary frame buffer memory until the second signal is output when a print start signal is input, at an initial stage, and the video data stored in the main frame buffer memory is transmitted to the auxiliary frame buffer memory as much as a set data transmission amount whenever the first signal is input, at a subsequent stage after the initial stage. There is also provided a video sync signal controller for controlling operation and interruption of the direct memory access controller according to a video data output control signal output from the engine and outputting the video clock sync signal.
It is preferred in the present invention that the auxiliary frame buffer memory outputs a third signal when a medium level set between the upper level and the lower level to a predetermined amount of the stored video data is reached, and the direct memory access controller controls the main frame buffer memory so that the video data stored in the main frame buffer memory is transmitted to the auxiliary frame buffer memory until the third signal is output, whenever the first signal is output at the subsequent stage.
Also, it is preferred in the present invention that the direct memory access controller controls the main frame buffer memory so that the video data stored in the main frame buffer memory is transmitted to the auxiliary frame buffer memory until the second signal is output, whenever the first signal is output at the
Kim Yong-Geun
Yun Jin-su
Evans Arthur G.
Samsung Electronics Co,. Ltd.
Sughrue & Mion, PLLC
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