Computer graphics processing and selective visual display system – Display driving control circuitry
Reexamination Certificate
2000-02-15
2003-09-09
Saras, Steven (Department: 2675)
Computer graphics processing and selective visual display system
Display driving control circuitry
C345S211000, C345S087000, C345S098000
Reexamination Certificate
active
06618043
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an image display device and an image display method, and particularly relates to an image display device driven with use of a precharge circuit that improves performance of write of image signals to data signal lines, and an image display method applied to the same.
BACKGROUND OF THE INVENTION
The following description will explain an active-matrix-type liquid crystal display device as an example of a conventional image display device. The image display device is, as shown in
FIG. 23
, composed of a pixel array ARY, a scanning signal line driving circuit (gate driver) GD, a data signal line driving circuit (data driver) SD, and a precharge circuit PC.
The pixel array ARY includes a plurality of scanning signal lines GL and data signal lines SL that cross each other, and each area defined by two adjacent scanning signal lines GL and two adjacent data signal lines SL has one pixel PIX, thereby causing a plurality of pixels PIX to be provided in a matrix form.
Each pixel PIX, as shown in
FIG. 24
, is composed of a switching element SW, a liquid crystal capacitor CL, and a supplemental capacitor CS. As shown in
FIG. 25
, in synchronization with timing signals such as a clock signal CKS and a data start signal SPS, the data signal line driving circuit SD samples image signals DAT inputted by an analog switch AS, then amplifies the sampled signals as required, and write the same into the data signal lines SL. In the FIG., N
1
through N
4
denote NAND circuits.
The scanning signal line driving circuit GD, as shown in
FIG. 26
, sequentially selects the scanning signal lines GL in synchronization with timing signals such as the clock signal CKG and the scanning start signal SPG, writes the image signals DAT written in the data signal lines SL into the pixels PIX by opening/closing the switching elements SW in the pixels PIX, and retains the written image signals DAT with use of the capacitors in the pixels. In
FIGS. 25 and 26
, SRs are shift resistors that sequentially output signals inputted thereto, in synchronization with a clock signal which is separately supplied thereto.
The precharge circuit PC samples a precharge reference potential PCV inputted thereto in synchronization with a precharge control signal (precharge control signal) PCC serving as a timing signal, and writes a signal of the precharge reference potential into the data signal lines before the image signals DAT are written therein.
By repeatedly carrying out the foregoing operations, an image is displayed on the pixel array ARY. A timing chart of these signals is shown in FIG.
27
.
In
FIG. 27
, the image signals DAT are inputted in synchronization with the clock signals CKS and /CKS and the data start signal SPS of the data signal line driving circuit. As a driving method of a horizontal line inversion type is adopted in this case, image signals with a negative polarity are written in lines corresponding to scanning signal lines GL
j
, while image signals with a positive polarity are written in lines corresponding to scanning signal lines GL
j+1
. During a flyback period (a period in which image signals are not inputted), the precharge control signal PCC is activated, and the data signal lines are precharged to have a precharge reference potential each. Here, the polarity of the precharge reference potential PCV is the same as that of the image signal DAT to be written next.
Recently, as the image display devices come to have further higher definition, the sampling rate of a data signal line driving circuit SD is increased. On the other hand, this entails a drawback in that write of image signals DAT into data signal lines becomes insufficient, thereby deteriorating quality of images. Then, adopted to cope with this drawback is a scheme in which data signal lines SL are precharged by means of a precharge circuit PC to a precharge reference potential (PCV), before image signals DAT are written into the data signal lines SL, so that deterioration of image quality is prevented.
FIG. 28
shows a concrete example of an arrangement of the precharge circuit. A precharge circuit
201
is provided with a reference signal input section
202
and a reference signal switching section
203
. The reference signal switching section
203
is provided with a switching element PAS group. More specifically, as shown in the figure, each data signal line SL is connected with one sampling-use switching element PAS, and each switching element is connected with the reference signal input section
202
so that the precharge reference potential PCV and the precharge control signal PCC are inputted to each switching element. The precharge circuit is intended to charge the data signal lines to the precharge reference potential PCV each at timings according to the precharge control signal PCC.
As shown in
FIG. 28
, however, the same number of switching elements PAS as that of data signal lines SL are connected with a line for supplying the precharge reference potential. To charge the data signal lines SL to the precharge reference potential within a small time as shown in the timing chart of
FIG. 27
, relatively great power is required. Therefore, a high-power element is used as the switching element PAS. Further, in the case where the switching element PAS group is controlled simultaneously for a precharging operation, a great quantity of charges move to the data signal lines SL, causing fluctuation of the precharge reference potential PCV.
If the potential having fluctuated is not stabilized to an appropriate level by the time when the sampling of the precharge reference potential is finished, this results in that the data signal lines SL are not charged to a sufficient level. This likely adversely affects the potential of the image data DAT written by the data signal line driving circuit SD to the data signal lines SL, thereby causing degradation of display.
Furthermore, if a quantity of current supplied from outside for producing the precharge reference potential is increased to suppress the fluctuation of the precharge reference potential (a driving force of the circuit for producing the precharge reference potential is increased), there arises another drawback in that power consumption increases.
Moreover, recently, decrease in an amplitude of an input signal supplied to a liquid crystal display device has been increasingly demanded. Conventionally, as shown in
FIG. 29
, a signal supplied from outside is fed to a circuit after an amplitude of the signal is increased by a level shifter such as a signal amplitude amplifying section
204
. Here, since the line for supplying the precharge control signal runs along one side of the liquid crystal display device and a great load is applied thereto, it is necessary to provide an extremely high-power buffer circuit
205
behind the level shifter. Such a high-power buffer circuit, disadvantageously, may tend to drastically increase power consumption while deteriorates reliability of the driving circuit.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an image display device and an image display method using a precharge circuit capable of suppressing fluctuation of a reference signal potential that is written into data signal lines to precharge the data signal lines while not augmenting power consumption.
To achieve the foregoing object, an image display device of the present invention, having a plurality of pixels in matrix that are defined by a plurality of data signal lines arranged in a row direction and a plurality of scanning signal lines arranged in a column direction, a data signal line driving circuit for feeding image signals to the data signal lines, and a scanning signal line driving circuit for feeding a scanning signal to the scanning signal lines, is characterized by comprising (i) a reference signal input section, to which at least one precharge reference potential is inputted, (ii) a control signal input section, to which at least one control signal is inputted, (iii) a plurality of sig
Kaise Yasuyoshi
Kubota Yasushi
Maeda Kazuhiro
Sakai Tamotsu
Washio Hajime
Conlin David G.
Edwards & Angell LLP
Nelson Alecia D.
Penny, Jr. John J.
Saras Steven
LandOfFree
Image display device and image display method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Image display device and image display method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Image display device and image display method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3052388