Computer graphics processing and selective visual display system – Computer graphics display memory system – Memory allocation
Reexamination Certificate
2007-09-18
2007-09-18
Hjerpe, Richard (Department: 2629)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Memory allocation
C345S087000, C345S098000, C345S099000, C345S100000, C345S530000, C345S531000, C345S533000, C345S539000, C345S541000
Reexamination Certificate
active
10833287
ABSTRACT:
When a contention is detected between a memory write address and a display read address in a memory circuit which stores display data, a host retry pulse generating circuit generates a display read signal and a display line data transfer signal based on a memory write clock, and supplies these to the memory circuit while supplying the display line data transfer signal to a line latch circuit. Alternatively, upon detection of the contention above, a same line re-display read processing circuit performs same line re-display read processing without moving to the next line, and supplies a display read signal and a display line data transfer signal to the memory circuit while supplying the display line data transfer signal to the line latch circuit.
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Kageyama Hiroyuki
Kaku Noriko
Kataoka Yumiko
Koizumi Takashi
Morinaga Hiroyuki
Hjerpe Richard
Stevens Davis Miller & Mosher LLP
Tran My-Chau T.
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