IIL semiconductor memory including arrangement for preventing in

Details IIL semiconductor memory including arrangement for preventing in IIL semiconductor memory including arrangement for preventing in

1983-03-17

1986-05-13

Popek, Joseph A.

Static information storage and retrieval

Systems using particular element

Flip-flop

365189, G11C 1100

Patent

active

045890960

ABSTRACT:
A semiconductor memory having memory cells in each of which emitter terminals and first collector terminals of two IIL unit circuits are cross-connected to each other, injector regions and a common emitter region of the two IIL unit circuits are respectively connected to upper and lower word lines, and second collectors of the IIL unit circuits are respectively connected to a pair of bit lines that are respectively connected through load elements to a power source higher in voltage than the lower word line. This serves to hold the bit line potential higher than the lower word line potential to ensure that transistors formed by the second collectors, the emitters and the bases are inversely operated to prevent information loss during a read operation.

REFERENCES:
patent: 4322820 (1982-03-01), Toyoda
patent: 4374431 (1983-02-01), Ono et al.

Affiliated with

Also associated with

Rating

IIL semiconductor memory including arrangement for preventing in does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with IIL semiconductor memory including arrangement for preventing in, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and IIL semiconductor memory including arrangement for preventing in will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1774229