Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Combined with field effect transistor
Reexamination Certificate
2000-01-07
2001-03-06
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
Combined with field effect transistor
C257S339000, C257S590000, C257S611000, C257S617000
Reexamination Certificate
active
06198115
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to insulated gate bipolar transistors (“IGBTs”)., and more specifically relates to an IGBT structure which has a reduced forward voltage drop, a reduced switching loss, and a process for its manufacture.
BACKGROUND OF THE INVENTION
ICBTs are well known devices having use in numerous switching applications. A typical IGBT and manufacturing process is described in British Patent 2,243,952 (GB IR-988). Two key characteristics of IGBTs are their forward voltage drop and their switching loss, both of which should be as low as possible. Thus, the forward voltage drop of a conventional IGBT formed in a silicon die is about 0.7 volts at the lowest. The switching speed of the device can be increased by the use of lifetime killing techniques such as irradiation, or the use of heavy metal doping, for example, gold and platinum, but this also increases its forward voltage drop.
Preferably, lifetime killing should be confined to the N
+
buffer layer of the IGBT junction pattern. Further, it is desirable to have lifetime killing minority collection sites uniformly distributed within a desired predetermined volume within the device crystal lattice.
BRIEF DESCRIPTION OF THE INVENTION
In accordance with a first feature of the invention, the interface between the P
+
main body and the N
+
buffer layer is intentionally damaged to produce lattice defects or dislocation sites which will selectively and uniformly collect heavy metal atoms such as platinum or gold which is diffused into the IGBT chip. These heavy metal atoms are then more uniformly distributed within some predetermined desired volume to cause a “leaky” junction at the P
+
/N
+
interface, thus reducing switching loss.
While the lattice can be selectively damaged in various ways, in accordance with a second aspect of the invention, the N
+
buffer layer of a monocrystalline silicon chip is formed to contain a small amount (about 1% by weight) of germanium, which has a depth of about 1 to 5 microns. This silicon/germanium N
+
region creates, in effect, a uniformly damaged lattice in the N
+
/P
+
junction area which permits the more uniform collection of and positioning of heavy metal lifetime killing atoms, thus increasing switching speed and reducing switching loss. Further, the use of the germanium in the silicon lattice in the boundary between the P
+
collector and the N
+
buffer layer lowers the minimum forward voltage drop of the device by approximately 150 mv. It should be noted that it is known to form a Si/Ge layer in an IGBT, as described in Z. Rodzimski et al., IEEE Trans. Electron Div. ED-35, 80 (1988). This however had the purpose of lifetime profiling over device depth and was not known to create a dislocation site to uniformly distribute heavy metal atoms.
REFERENCES:
patent: 5661314 (1997-08-01), Merrill et al.
patent: 5766966 (1998-06-01), Ng
patent: 6008092 (1999-12-01), Gould
Francis Richard
Merrill Perry L.
Chaudhuri Olik
International Rectifier Corp.
Ostrolenk Faber Gerb & Soffen, LLP
Pham Hoai
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