Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
1999-06-15
2002-06-11
Dharia, Rupal (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S104000, C710S105000, C710S300000, C370S487000
Reexamination Certificate
active
06405275
ABSTRACT:
BACKGROUND OF THE INVENTION
The IEEE (Institute of Electrical and Electronics Engineers) Computer Society published the IEEE STD 1394-1995 entitled, “IEEE Standard for a High Performance Serial Bus.” This standard and its follow-on supplements define a serial data bus with a cable and backplane environment, non-cyclic topology, scalable data rates starting at 100 Megabits per second, and the cable arbitration system uses a self-configuring hierarchical request/grant protocol that supports hot plugging and widely varying physical topologies.
In addition to standard read/write and lock transactions, the high performance serial bus defined in IEEE STD 1394-1995 (hereinafter referred to as the IEEE1394 bus) provides extensive time-based services. These services include isochronous data transport (guaranteed latency and bandwidth) and an accurate sub-microsecond global timebase for synchronizing events and data. It is the isochronous service provided by the IEEE1394 bus that make it an attractive interconnect between consumer audio/video equipment.
The International Electrotechnical Commission (IEC) International Standard IEC 61883-1 entitled “Digital Interface For Consumer Audio/Video Equipment” defines the general packet format, data flow management, and connection management for audio/visual data, and also the general transmission rules for control commands. Transmission of Digital Video Cassette Recording (DVCR) system data, MPEG2 transport streams, and audio and music data transmission are among the data flows that fall into the scope of the above-mentioned IEC standard. These data transmissions utilize the isochronous service provided by the IEEE1394 bus.
The packet format defined by IEC 61883-1 for isochronous data transmissions is referred to as common isochronous packet (CIP) format. The CIP format utilizes the isochronous packet format defined by IEEE1394, has allocated a particular tag value, and includes a header (hereinafter referred to as a CIP header) placed at the beginning of the data field of an IEEE1394 isochronous packet, immediately followed by zero or more data blocks. The CIP header contains fields that specify stream dependent variables such as a format identifier, data block size, an indication of a time stamp, and a format dependent time stamp field.
The time stamp in a common isochronous packet is used for application dependent synchronization needs, such as video frame synchronization in DVCR streams. Typically, this time stamp indicates to a receiver when to release the packet to its real-time application, which in some cases has strong requirements on the timing and jitter of the deliver of individual packets or blocks of packets. Smoothing buffers often meet these requirements by holding received data until the IEEE1394 bus time matches the time stamp value, and there are typically rules associated with late packets. Hence, the time stamp value should be greater than or equal to the expected packet arrival time at the receiver, and the offset placed in the time stamp at transmission is attained from a worst case transmission delay calculation.
Various real-time applications that transmit CIP streams (those that comply with IEC 61883-1) have little problems with the inclusion of time stamps. These transmitters may construct and insert CIP headers and format the data per IEC 61883-1, and have knowledge of IEEE1394 bus time during this construction. A hard coded or programmable offset is added to the IEEE1394 bus time to construct the time stamp to account for deliver delay.
CIP streams may be transmitted to the IEEE1394 bus from a personal computer (PC) system, possibly from a DVCR editing application. In this environment there typically exists what is referred to as an IEEE1394 host controller that connects a PC host bus to a PHY/Link or cable interface defined by IEEE1394. Software executing on the PC host system generates the CIP streams and queues the packets through the operating system to be transmitted by the host controller. Software executing on platforms with typical host controllers must keep track of IEEE1394 bus time to insert time stamps, and the bus time is typically ascertained by reading a host controller register.
Unfortunately, there are several problems that present themselves when software attempts to insert time stamps in CIP headers. One such problem is due to the fact that IEEE1394 bus time can change due to a bus reset event, and a race condition thus exists between the last read of bus time and the time a packet or packets are queued to the host controller for transmission. The potentially bogus time stamp may not be catastrophic, but may yield a lower quality experience. For example, a dropped frame or two of video may not dramatically affect the end user's experience, but a dropped frame or two of music data could yield an audible and undesirable result.
Since reading the IEEE1394 bus time several times a second (up to 30 for full motion video) can become a performance burden, software that generates CIP streams may attempt to interpolate the time stamp field. In this case a transient software latency condition that causes one frame to be delivered late may affect the entire stream catastrophically.
Although some CIP stream receivers do not have strong requirements on the timing and jitter of CIP packet delivery, there are formats that currently do have these requirements, and it is expected that formats will be created that will exhibit these requirements. CIP streams generated via software using operating systems that are not real-time in nature may have performance problems due to unexpected or undesirable operating system latencies.
A strong desire exists to solve the foregoing problems associated with CIP stream transmission from platforms that implement a host controller and operating system that is not real-time in nature.
SUMMARY OF THE INVENTION
In accordance with the present invention, there is disclosed an IEEE1394 host controller which connects a computer to the IEEE1394 bus via an input/output data bus, the IEEE1394 bus automatically inserting time stamp information, based upon the host controller concept of IEEE1394 bus time, into isochronous packets.
Further in accordance with the present invention, there is disclosed a method of calculating an offset to add to IEEE1394 bus time when automatically inserting time stamp information into isochronous packets. The method utilizes the host controller functionality to start an isochronous transmit stream at a value of IEEE1394 bus time, the offset being the difference between the transmit stream start time and the first time stamp present in the data stream.
The CIP header enhancements for host controllers described here can remove the factor of IEEE1394 bus time from the algorithm that generates the isochronous stream CIP headers. This invention can prevent unexpected software latencies in the operating system from providing incorrect time stamps, which can result in catastrophic performance to the end user.
This invention can remove the additional host bus bandwidth and packet creation overhead required in reading IEEE1394 bus time from the host controller before queuing packets for transmission through the operating system. The race condition that exists between the last read of IEEE1394 bus time from the host controller and the actual time (bus time can change) the packet is transmitted can be removed with this invention.
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Mitchell Danny L.
Morrow Neil G.
Brady III Wade James
Dharia Rupal
Stewart Alan K.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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