IEEE 1149.1 tap instruction scan with augmented TLM scan mode

Details IEEE 1149.1 tap instruction scan with augmented TLM scan mode IEEE 1149.1 tap instruction scan with augmented TLM scan mode

2007-05-01

2007-05-01

Baderman, Scott (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S031000, C714S041000, C714S048000

Reexamination Certificate

active

10772982

ABSTRACT:
An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.

REFERENCES:
patent: 4698750 (1987-10-01), Wilkie et al.
patent: 5689516 (1997-11-01), Mack et al.
patent: 5737760 (1998-04-01), Grimmer et al.
patent: 6073254 (2000-06-01), Whetsel
patent: 6134675 (2000-10-01), Raina
patent: 6142683 (2000-11-01), Madduri

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