Idle power reduction for state machines

Details Idle power reduction for state machines Idle power reduction for state machines

2006-06-06

2006-06-06

Browne, Lynne H. (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S300000, C713S320000

Reexamination Certificate

active

07058832

ABSTRACT:
A state machine provides a power reducing capability by turning off a clock signal to a memory which stores the state of the state machine. Preferably, the state machine is connected to receive information from an external circuit, typically a system to be controlled by the state machine. The state machine includes a programmable memory in which each row stores a word representing output information as a sequence of bits. It also includes a register which stores the state of the state machine when the memory is not active. The state machine includes a selection circuit which selects a next state of the state machine. When the next state of the state machine is selected to be the same as the previous state the clock signal to the memory is turned off, enabling reduced power consumption by the state machine.

REFERENCES:
patent: 5349670 (1994-09-01), Agrawal et al.
patent: 5778251 (1998-07-01), Kuroiwa et al.
patent: 6073223 (2000-06-01), McAllister et al.

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