Identification circuit for indicating redundant row or column su

Details Identification circuit for indicating redundant row or column su Identification circuit for indicating redundant row or column su

1992-04-10

1993-10-12

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Bad bit

365201, 3652257, 371 103, G11C 800

Patent

active

052532089

ABSTRACT:
An identification circuit for identifying how many redundant rows and columns have been substituted for normal rows and columns in a memory device is disclosed. Column and row identifying circuits are used, respectively, with each circuit having a plurality of fuses with each fuse having a pair of leads and a plurality of resistive elements with each resistive element connected, in series, to a lead of one of the fuses and with the remaining lead of the fuse connected to a common lead. Each resistive element is connected to a ground to permit each interconnected fuse and resistive element to be connected in parallel. Thus, in use, each fuse intentionally opened in assembly of the memory device indicates that a malfunctioning single normal row/column has been substituted with a redundant row/column and upon sealing the memory device, substitution is indicated by application of a voltage to each circuit to form a current therein which is related to a number of substituted rows/columns present in the memory device.

REFERENCES:
patent: 4389715 (1983-06-01), Eaton et al.
patent: 4573146 (1986-02-01), Graham et al.
patent: 4586170 (1986-04-01), O'Toole et al.
patent: 4641286 (1987-02-01), Shimotori et al.
patent: 4654830 (1987-03-01), Chua et al.
patent: 4689494 (1987-08-01), Chen et al.
patent: 4985866 (1991-01-01), Nakaizumi

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