IC with two state machines connected to serial scan path

Details IC with two state machines connected to serial scan path IC with two state machines connected to serial scan path

2000-12-21

2004-08-17

Iqbal, Nadeem (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S729000

Reexamination Certificate

active

06779133

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to testing electrical circuits via serial scan access and, more particularly, to testing techniques which allow circuits to be serially tested in a more efficient manner than achieved using conventional serial test approaches.
BACKGROUND OF THE INVENTION
Test bus interfaces exist which allow serial data to be shifted in and out of integrated circuits to facilitate testing of the logic in the device. These buses are designed primarily to transfer a single pattern of serial data into and out of a selected scan path surrounding the circuit under test once per shift operation. Depending on the complexity of the circuit, potentially thousands or hundreds of thousands of shift operations may be required to fully test the circuit. Having to repeat a shift operation multiple times to transfer test data patterns into and out of the circuit being tested is time consuming.
IEEE 1149.1 Test Bus and Architecture Description
While many types of test buses exist, the IEEE 1149.1 test bus will be used in this disclosure to describe the advantages of the invention. The IEEE standard IC test bus and architecture described in the 1149.1 specification is shown in FIG.
1
. This architecture has been developed to provide a standard method to serially access serial test registers in IC designs to facilitate testing. This test architecture, shown in
FIG. 1
, consists of an instruction register (IREG), a set of data registers (DREG) referred to as Bypass, DREG
1
, and DREG
2
, and a test interface referred to as a Test Access Port (TAP). While only one IREG may be implemented in the architecture, any number of DREGs can be included. Each DREG of
FIG. 1
is associated with the input and output boundary of a circuit in the IC to enable serial testing of the circuit. The Bypass DREG is not used for testing, but rather for providing an abbreviated scan path through the IC when testing of circuits, associated with DREG
1
and DREG
2
, is not required.
The IREG and DREGs exist on separate scan paths arranged in parallel between the test data input pin (TDI)
102
and test data output pin (TDO)
116
. During IREG scan operations the TAP receives external control via the test mode select (TMS)
104
and test clock (TCK)
106
and outputs internal control via the control bus
108
to shift data through the IREG from the TDI input to the TDO output. Similarly, DREG scan operations are accomplished by the TAP receiving external control on the TMS and TCK input and outputting internal control on control bus
108
to shift data through the selected DREGs. Control for selecting one of the DREGs comes from the instruction shifted into the IREG and is output from the IREG via control bus
110
. The control output on bus
110
is input to all DREGs and selects one for shifting. Control bus
110
is also input to multiplexer 1 to couple the serial output of the selected DREG to the TDO output.
The TAP is a finite state machine which responds to a scan access protocol input via the TMS and TCK inputs. The purpose of the TAP is to respond to the input scan access protocol to shift data through either the IREG or DREG. The TAP is clocked by the TCK input and makes state transitions based on the TMS input. The TAP state diagram is shown in FIG.
2
and consists of sixteen states: test logic reset (TLRESET), run test/idle (RT/IDLE), select data register scan (SELDRS), select instruction register scan (SELIRS), capture data register (CAPTUREDR), shift data register (SHIFTDR), exit
1
data register (EXITDRr), pause data register scan (PAUSEDR), exit
2
data register (EXIT
2
DR), update data register (UPDATEDR), capture instruction register (CAPTUREIR), shift instruction register (SBIFTIR), exit
1
instruction register (EXIT
1
IR), pause instruction register Scan (PAUSEIR), exit
2
instruction register (EXIT
2
IR), and update instruction register (UPDATEIR).
At power up or during normal operation of the host IC, the TAP will be in the TLRESET state. In this state, the TAP issues a reset signal that places all test logic in a condition that will not impede normal operation of the host IC. When test access is required, a protocol is applied via the TMS and TCK inputs, causing the TAP to exit the TLRESET state and enter the RT/IDLE state. In
FIG. 2
, the TMS input that causes movements between the TAP states is indicated by a logic 0 or 1. TCK is the clock that causes the TAP state controller to transition from state to state.
From the RT/IDLE state, an instruction register scan protocol can be issued to transition the TAP through the SELDRS and SELIRS states to enter the CAPTUREIR state. The CAPTUREIR state is used to preload the IREG with status data to be shifted out of the TDO output pin. From the CAPTUREIR state, the TAP transitions to either the SHIFTIR or EXIT
1
IR state. Normally the SHIFTIR will follow the CAPTUREIR state so that the preloaded data can be shifted out of the IREG for inspection via the TDO output while new data is shifted into the IREG via the TDI input. Following the SHIFTIR state, the TAP either returns to the RT/IDLE state via the EXIT
1
IR and UPDATEIR states or enters the PAUSEIR state via EXIT
1
IR. The reason for entering the PAUSEIR state would be to temporarily suspend the shifting of data through the IREG. From the PAUSEIR state, shifting can be resumed by re-entering the SHIFTIR state via the EXIT
2
IR state or it can be terminated by entering the RT/IDLE state via the EXIT
2
IR and UPDATEIR states.
From the RT/IDLE state, a data register scan protocol can be issued to transition the TAP through the SELDRS state to enter the CAPTUREDR state. The CAPTUREDR state is used to preload the selected DREG with data to be shifted out of the TDO output pin. From the CAPTUREDR state, the TAP transitions to either the SHIFTDR or EXIT
1
DR state. Normally the SHIFTDR will follow the CAPTUREDR state so that the preloaded data can be shifted out of the DREG for inspection via the TDO output while new data is shifted into the DREG via the TDI input. Following the SHIFTDR state, the TAP either returns to the RT/IDLE state via the EXIT
1
DR and UPDATEDR states or enters the PAUSEDR state via EXIT
1
DR. The reason for entering the PAUSEDR state would be to temporarily suspend the shifting of data through the DREG. From the PAUSEDR state, shifting can be resumed by re-entering the SHIFTDR state via the EXIT
2
DR state or it can be terminated by entering the RT/IDLE state via the EXIT
2
DR and UPDATEDR states.
In application, any number of ICs that implement the IEEE 1149.1 architecture can be serially connected together at the circuit board level as shown in FIG.
3
. Similarly, any number of circuit boards can be connected together to further increase the number of ICs serially connected together. The ICs in
FIG. 3
are connected serially via their TDI input and TDO output pins from the first to the last IC. Also each IC receives TMS and TCK control inputs from a test bus controller. The test bus controller also outputs serial data to the TDI input of the first IC in the serial path and receives serial data from the TDO of the last IC in the serial path. The test bus controller can issue control on the TMS and TCK signals to cause all the ICs to operate together to shift data through either their internal IREG or DREGs, according to the TAP protocol procedure previously described.
During IREG shift operations the total length of the shift path is equal to the sum of the bits in each ICs IREG. For example, if one hundred ICs are in the serial path (
FIG. 3
) and each ICs IREG is 8 bits long the number of bits that must be shifted per IREG shift operation is eight hundred. Similarly, during DREG shift operations the total length of the serial path is equal to the sum of the bits in each ICs selected DREG. If the Bypass DREG is selected in each IC the total number of bits shifted during a DREG scan is equal to the number of ICs times 1 bit, since the Bypass DREG is only one bit long. Each IC can select a different DREG by loading in different instr

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