IC with built-in self-test and design method thereof

Details IC with built-in self-test and design method thereof IC with built-in self-test and design method thereof

2005-09-27

2005-09-27

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Converter calibration or testing

C341S118000, C341S155000, C714S733000, C714S734000

Reexamination Certificate

active

06950046

ABSTRACT:
IC with built-in self-test and design method thereof. The IC comprises an SD-ADC and a Dft circuit. The Dft circuit uses a digital stimulus signal to solve the deadlock problem of the on-chip analog testing and avoid thermal noise. Moreover, according to the design method of the IC, circuits having different specification can use the Dft circuit without performance degradation for original SD-ADC.

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Luo et al., “Testable Sigma-Delta ADC Design without Performance Degradation,” VLSI Design CAD Symposium, Aug. 12, 2003.

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