IC wafer-probe testable flip-chip architecture

Details IC wafer-probe testable flip-chip architecture IC wafer-probe testable flip-chip architecture

1997-12-12

1999-07-06

Picardat, Kevin M.

Semiconductor device manufacturing: process

With measuring or testing

Electrical characteristic sensed

438 14, 438 17, G01R 3126, H01L 2166

Patent

active

059207655

ABSTRACT:
The uppermost metal layer (metal-one) on a flip-chip packageable IC is modified to include at least one VCC pad, at least one ground pad, and at least one and preferably five test pads. Each pad is sized to be probe wafer-contactable, is and electrically coupled to appropriate vias formed in the IC. During IC fabrication but before the destination layer is fabricated, the IC is tested using a wafer probe that couples appropriate signals and power to the pads formed on the metal-one layer. If testing discloses a bug, it is possible to modify the IC metal-one traces, e.g., using FIB and then re-wafer probe test the IC. An insulating layer and destination layer may then be fabricated over what is known to be a good IC, and re-testing may occur. In this fashion, debugging diagnostics are made using testable ICs, and any metal-one revision may be tried and confirmed before changing the metal-one pattern for mass produced ICs. Preferably the IC includes a JTAG-compatible controller, and the metal-one layer includes five JTAG pads.

REFERENCES:
patent: 5040151 (1991-08-01), Miyawaki et al.
patent: 5279975 (1994-01-01), Devereaux et al.
patent: 5286656 (1994-02-01), Keown et al.
patent: 5355369 (1994-10-01), Greenberger et al.
patent: 5781560 (1998-07-01), Kawano et al.

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