IC memory testing apparatus

Details IC memory testing apparatus IC memory testing apparatus

1992-11-13

1994-03-01

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Testing

371 211, 371 212, G01R 3128

Patent

active

052914496

ABSTRACT:
An IC memory testing apparatus comprises a pattern generating circuit, a decision circuit, a first-in memory circuit which stores the defect data of a IC memory under test and simultaneously reads the resulting data. A latch circuit is also used to shorten the testing time. The resulting information about the defective cell of the tested IC memory is stored and read out during the test, with the memory circuit executing a storing operation for the address of defective cell data and simultaneously executing a reading operation for the data having been stored. The time periods required for the reading and writing operations are set independently of each other, and the operation frequency of the memory circuit is less than for testing the memory to be tested.

REFERENCES:
patent: 4414665 (1983-11-01), Kimura et al.
patent: 4873666 (1989-10-01), Lefebvre et al.
patent: 5062109 (1991-10-01), Ohshima et al.

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