IC layout having topological routes

Details IC layout having topological routes IC layout having topological routes

2005-08-09

2005-08-09

Whitmore, Stacy A. (Department: 2812)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

06928633

ABSTRACT:
Some embodiments of the invention provide an integrated circuit (“IC”) design layout that includes topological routes. This layout includes several nets, each with a set of routable elements in the IC design-layout region. For each net, this layout also includes a topological route that connects the net's routable elements. Each topological route is a route that represents a set of diffeomorphic geometric routes. In some embodiments, the IC layout further includes a topological graph that represents the IC design layout topologically. The topological graph includes several topological items including a set of items for each net that represent the net's routable elements. Each net's topological route specifies an associated set of items in the topological graph.

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