IC layout buffer insertion method

Details IC layout buffer insertion method IC layout buffer insertion method

2006-04-11

2006-04-11

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07028280

ABSTRACT:
An integrated circuit (IC) layout system designs nets for interconnecting cells forming modules of a hierarchical IC design. Each module is defined as having one or more ports through which the nets extend when linking cells forming different modules. The layout system automatically inserts buffers into selected segments of the nets to reduce signal path delays through the nets and assigns the inserted buffers to selected modules. However the layout system inserts buffers only into those net segments for which a buffer insertion would not alter the number of ports any module needs to accommodate the net.

REFERENCES:
patent: 6412101 (2002-06-01), Chang et al.
patent: 6425114 (2002-07-01), Chan et al.
patent: 6510542 (2003-01-01), Kojima
patent: 6581199 (2003-06-01), Tanaka
patent: 2002/0162086 (2002-10-01), Morgan
patent: 2003/0163795 (2003-08-01), Morgan et al.

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