Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1997-02-27
2000-04-11
Everhart, Caridad
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438745, 438906, 438692, H01L 21461
Patent
active
060487895
ABSTRACT:
An integrated circuit manufacturing method uses chemical-mechanical polishing (CMP) to planarize a nonplanar submetal (or intermetal) silica dielectric layer. The planarized device is cleaned with an aqueous solution of ammonium hydroxide and citric acid. Exposed hydrated silica is etched using mixture of nitric and hydrofluoric acids, freeing embedded contaminants from the CMP slurry. The hydrofluroic acid is the etching agent, while the nitric acid combines with the freed contaminants to render water soluble products. They are thus carried away in an aqueous rinse, whereas otherwise they might recontaminate the device. A metal interconnect structure is formed on the etched oxide by forming contact apertures, depositing metal, and patterning the metal. The method can be applied also to nonplanar intermetal dielectrics and subsequent metal interconnect layers. The result is an integrated manufacturing method with higher yields and a more reliable manufactured integrated circuit.
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Burggraaf, Pieter, "Keeping the `RCA` in Wet Chemistry Cleaning", Semiconductor International, Jun. 1994, pp. 86, 87, 88, 90.
Fury, Michael A., "Emerging developments in CMP for semiconductor planarization", Solid State Technology, Apr., 1995, pp. 47, 48, 50, 52.
Kern Jr., Frderick W., "Mechanism for Metallic Contamination of Semiconductor Wafer Surfaces", abstractd 304, pp. 498-499.
Oki, I, H. Shibayama, and A. Kagisawa, "Contamination Reduction in Dilute HF by Adding Hcl" Abstract No. 289, pp. 474-475.
Bellows Craig A.
Parmantie Walter D.
Vines Landon B.
Anderson Clifton L.
Everhart Caridad
VLSI Technology Inc.
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