Semiconductor device manufacturing: process – With measuring or testing – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2001-05-23
2003-06-10
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
With measuring or testing
Packaging or treatment of packaged semiconductor
C438S012000, C438S017000
Reexamination Certificate
active
06576484
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to semiconductor device assemblies and, more particularly, to techniques for analyzing and debugging circuitry associated with a flip chip integrated circuit die.
BACKGROUND OF THE INVENTION
Recent technological advances in the semiconductor industry have permitted dramatic increases in circuit density and complexity, and commensurate decreases in power consumption and package sizes for integrated circuit devices. Single-chip microprocessors now include many millions of transistors operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages. A byproduct of these technological advances has been an increased demand for semiconductor-based products, as well as increased demand for these products to be fast, reliable, and inexpensive. These and other demands have led to increased pressure to manufacture a large number of semiconductor devices at an efficient pace while increasing the complexity and improving the reliability of the devices.
As the manufacturing processes for semiconductor devices and integrated circuits increase in difficulty, methods for manufacturing, testing and debugging these devices become increasingly important. Not only is it important to ensure that individual chips are functional, it is also important to ensure that batches of chips perform consistently. In addition, the ability to detect a defective manufacturing process early is helpful for reducing the possibility of manufacturing a defective device. It is also helpful to be able to perform the manufacture, testing and debugging of integrated circuits in an efficient and timely manner.
To increase the number of pad sites available for a die, to reduce the electrical path to the pad sites, and to address other problems, various chip-packaging techniques have been developed. One of these techniques is referred to as controlled collapse chip connection or “flip-chip” packaging. With packaging technology, bonding pads of the die include metal (solder) bumps. Electrical connection to the package is made when the die is “flipped” over and soldered to the package. Each bump connects to a corresponding package inner lead. The resulting packages are low profile and have low electrical resistance and a short electrical path. The output terminals of the package, which are sometimes ball-shaped conductive bump contacts, are typically disposed in a rectangular array. These packages are occasionally referred to as “Ball Grid Array” (BGA) packages. Alternatively, the output terminals of the package may be pins and such packages are commonly known as pin grid array (PGA) packages.
Once the die is attached to such a package, the back side portion of the die remains exposed. The transistors and other circuitry are generally formed in a very thin epitaxially grown silicon layer on a single crystal silicon wafer from which an individual die is later singulated. The side of the die including the epitaxial layer and containing the transistors and other circuitry is often referred to as the circuit side or front side of the die. The circuit side of the die is positioned very near the package and opposes the back side of the die. Between the back side and the circuit side of the die is bulk silicon. The positioning of the circuit side near the package provides many of the advantages of the flip-chip. However, orienting the die with the circuit side face down on a substrate is disadvantageous in some instances. Due to this orientation of the die, the transistors and circuitry near the circuit side are not directly accessible for testing, modification or other purposes. Therefore, access to the transistors and circuitry near the circuit side is limited.
Analysis of a flip-chip die may be performed through the back side using techniques such as scanning electron microscopy, scanning optical microscopy, or x-ray. These techniques often require the back side of the die to be thinned before they can be effectively employed. However, one function of the back side bulk silicon layer is to serve as a heat sink for the flip-chip die. When the tightly packed circuitry of the die is operated at high speeds it generates heat which if not dissipated causes the chip to overheat. Removal or other modifications to the back side bulk silicon layer that adversely effect the heat dissipating characteristics of the die exacerbate the overheating tendencies of the die.
Another method of testing and analysis of circuitry in an integrated circuit includes locating defective portions of the circuitry by controlling inputs to the die and monitoring outputs in order to determine if the die is operating as designed. This testing is facilitated by the use of testing circuitry located in a die, such as built-in self test (BIST) circuitry including redundant or replacement circuitry. However, concerns about maximizing use of space while minimizing manufacturing costs precludes putting extensive circuitry into a die for the sole purpose of testing. Additionally, constructing a limited number of “test dies” containing testing circuitry is not effective because the test die will have a different design then the standard die and will not necessarily function in the same manner.
SUMMARY OF THE INVENTION
The present invention is directed to flip-chip die analysis using a method that improves the thermal conductivity of the die, constructs circuitry in the back side of the thermal conductivity enhanced die and utilizes said circuitry to perform die analysis. The present invention is exemplified in a number of implementations and applications, aspects of which are summarized below.
In one example embodiment of the present invention, a portion of a back side of a flip-chip type integrated circuit die is formed having a thermal conductivity enhancing material. An epi-layer (epitaxial layer) of silicon is formed in the back side of the die. Circuitry is constructed in the epi-layer and electrically coupled to circuitry in the circuit side of the die. The circuit side circuitry and the newly formed back side circuitry are operated in conjunction with one another and used for analyzing the die. The heat from the operation of the circuit side circuitry and the additional heat generated by the operation of the back side circuitry is dissipated by the thermal conductivity enhancing material. In this manner, challenges to die analysis involving circuit construction and heat dissipation, such as those discussed in the Background, are met. Some of the example benefits realized by the present invention include the ability to selectively couple the test circuitry to portions of circuitry in the die, the ability to operate the die at high speeds and under stress as facilitated by the heat removal, and the ability to repair dies after or during analysis.
In another example embodiment of the present invention, a system is adapted for analyzing a semiconductor die. The system includes a formation arrangement adapted to form a backside having a thermal conductivity enhancing material such that heat generated during operation of the die is dissipated. A deposition arrangement is adapted to form a silicon epi-layer in the back side of the die. A construction arrangement is adapted to construct circuitry in the epi-layer, and a coupling arrangement is adapted to electrically couple the constructed circuitry with pre-existing circuitry in the circuit side of the die. The newly formed circuitry is adapted to operate in conjunction with the thermal conductivity enhancing material in a manner that facilitates analysis of the die via an analysis arrangement adapted to monitor the operation of the die and analyze the die therefrom.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description that follow more particularly exemplify these embodiments.
REFERENCES:
patent: 3656232 (1972-04-01), Hinchey
patent: 4782381 (1988-11-01), Ruby e
Birdsley Jeffrey D.
Bruce Michael R.
Davis Brennan V.
Ring Rosalinda M.
Stone Daniel L.
Advanced Micro Devices , Inc.
Lebentritt Michael S.
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