IC conductor capacitance estimation method

Details IC conductor capacitance estimation method IC conductor capacitance estimation method

2005-08-02

2005-08-02

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06925619

ABSTRACT:
An RC extraction tool estimates capacitances of conductors residing along parallel grid lines on each of a set vertically stacked layers of insulating material of an IC based on data contained in a IC layout file describing positions of structures forming the IC. The tool initially processes the layout file to generate a separate database for each layer. Each database includes a separate table for each grid line on its corresponding layer, and each table includes a separate entry for each conductor residing along that grid line containing data indicating dimensions and a position of its corresponding conductor along that grid line. The tool processes the databases for each layer in ascending order to estimate capacitances between conductors on that layer and to generate set of data structures mapping the amount of conductor surface area on that layer to areas of layers above that layer, and to areas of layers below that layer in which conductors reside. The tool then processes the data structures to estimate capacitances between conductors on nearby layers.

REFERENCES:
patent: 5831870 (1998-11-01), Folta et al.
patent: 6360350 (2002-03-01), Gabele et al.
patent: 6618846 (2003-09-01), Cheng
patent: 2003/0237063 (2003-12-01), Kauth et al.
patent: 2004/0225975 (2004-11-01), Pramono

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