IC compaction system

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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Details

C716S030000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

11051074

ABSTRACT:
An integrated circuit (IC) layout includes an arrangement of instances of cells, wherein each cell describes a separate corresponding electronic device to be incorporated into the IC. An internal layout of each cell includes one or more objects corresponding to portions of IC material that are to form the corresponding electronic device, and the shape and position of each object within the cell layout represents the shape and position of the corresponding portion of IC material within the corresponding electronic device. When a dimension or position of an object within a cell's internal layout can be altered without affecting the behavior of the electronic device the cell describes, a device rule is created for that cell to indicate any constraint on that object's dimension or relative position. The IC layout is then compacted both by moving cell instances closer together, and also by altering internal layouts of cell instances in a manner consistent with their device rules.

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patent: 2005/0188338 (2005-08-01), Kroyan et al.

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